Travelled to:2 × France
3 × Germany
Collaborated with:M.Renovell J.Figueras Y.Zorian L.Lopez D.Née S.Bernardini P.Masson F.Clermidy N.Jovanovic S.Onkaraiah H.Oucheikh O.Thomas O.Turkyilmaz E.Vianello M.Bocquet C.Metra G.A.Mojoli S.Pastore D.Salvi G.R.Sechi
Talks about:test (3) configur (2) logic (2) fpga (2) base (2) interconnect (1) technolog (1) capacitor (1) techniqu (1) structur (1)
Person: Jean Michel Portal
DBLP: Portal:Jean_Michel
Contributed to:
20142005200419991998Wrote 6 papers:
- DATE-2014-ClermidyJOOTTVPB #question
- Resistive memories: Which applications? (FC, NJ, SO, HO, OT, OT, EV, JMP, MB), pp. 1–6.
- DATE-2005-LopezPN #embedded #metric
- A New Embedded Measurement Structure for eDRAM Capacitor (LL, JMP, DN), pp. 462–463.
- DATE-v2-2004-BernardiniPM
- A Tunneling Model for Gate Oxide Failure in Deep Sub-Micron Technology (SB, JMP, PM), pp. 1404–1405.
- DATE-1999-RenovellPFZ #configuration management #interface #logic #testing
- Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA’s (MR, JMP, JF, YZ), pp. 618–622.
- DATE-1998-MetraRMPPFZSS #novel #testing
- Novel Technique for Testing FPGAs (CM, MR, GAM, JMP, SP, JF, YZ, DS, GRS), pp. 89–94.
- DATE-1998-RenovellPFZ #approach #configuration management #logic
- RAM-Based FPGA’s: A Test Approach for the Configurable Logic (MR, JMP, JF, YZ), pp. 82–88.