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Travelled to:
2 × France
2 × Germany
4 × USA
Collaborated with:
M.Shafique J.Henkel F.Kriebel D.Sun P.V.Aceituno T.Li J.A.Ambrose S.Parameswaran L.Bauer H.Zhang B.Zatt D.Gnad J.Chen S.Radhakrishnan R.G.Ragel
Talks about:
reliabl (6) error (6) resili (5) variabl (4) adapt (4) processor (3) soft (3) instruct (2) configur (2) silicon (2)

Person: Semeen Rehman

DBLP DBLP: Rehman:Semeen

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DAC 20122012
DATE 20122012

Wrote 12 papers:

DAC-2015-GnadSKRSH #named #variability
Hayat: harnessing dark silicon and variability for aging deceleration and balancing (DG, MS, FK, SR, DS, JH), p. 6.
DATE-2015-KriebelRSASH #analysis #combinator #configuration management #fault #named #performance
ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuits (FK, SR, DS, PVA, MS, JH), pp. 824–829.
DAC-2014-HenkelBZRS #architecture #dependence #multi
Multi-Layer Dependability: From Microarchitecture to Application Level (JH, LB, HZ, SR, MS), p. 6.
DAC-2014-KriebelRSSH #adaptation #fault #named
ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era (FK, SR, DS, MS, JH), p. 6.
DAC-2014-RehmanKSSH #adaptation #code generation #dependence #named #process #reliability
dTune: Leveraging Reliable Code Generation for Adaptive Dependability Tuning under Process Variation and Aging-Induced Effects (SR, FK, DS, MS, JH), p. 6.
DATE-2014-RehmanKSH #compilation #reliability
Compiler-driven dynamic reliability management for on-chip systems under variabilities (SR, FK, MS, JH), pp. 1–4.
DAC-2013-LiSARHP #adaptation #embedded #fault #named #runtime
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors (TL, MS, JAA, SR, JH, SP), p. 7.
DAC-2013-ShafiqueRAH #fault #optimisation #reliability
Exploiting program-level masking and error propagation for constrained reliability optimization (MS, SR, PVA, JH), p. 9.
DATE-2013-LiSRRRAHP #configuration management #named
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors (TL, MS, SR, SR, RGR, JAA, JH, SP), pp. 707–712.
DATE-2013-RehmanSAKCH #hardware #reliability
Leveraging variable function resilience for selective software reliability on unreliable hardware (SR, MS, PVA, FK, JJC, JH), pp. 1759–1764.
DAC-2012-RehmanSH #compilation #scheduling
Instruction scheduling for reliability-aware compilation (SR, MS, JH), pp. 1292–1300.
DATE-2012-ShafiqueZRKH #adaptation #power management
Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length Coding (MS, BZ, SR, FK, JH), pp. 697–702.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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