BibSLEIGH corpus
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Travelled to:
1 × India
1 × Spain
2 × USA
Collaborated with:
R.R.Iyer L.Zhao R.Iyer A.Kumar R.Huggahalli N.Madan D.Newell R.Balasubramonian X.Jiang N.Muralimanohar A.N.Udipi A.K.Mishra Z.Fang S.Srinivasan P.Brett C.R.Das M.Upton Y.Solihin
Talks about:
cach (4) character (2) access (2) microprocessor (1) architectur (1) reconfigur (1) hierarchi (1) platform (1) communic (1) asymmetr (1)

Person: Srihari Makineni

DBLP DBLP: Makineni:Srihari

Contributed to:

HPCA 20112011
HPCA 20102010
HPCA 20092009
HPCA 20042004

Wrote 5 papers:

HPCA-2011-JiangMZIFSMBD #named #scheduling #symmetry
ACCESS: Smart scheduling for asymmetric cache CMPs (XJ, AKM, LZ, RI, ZF, SS, SM, PB, CRD), pp. 527–538.
HPCA-2010-JiangMZUIMNSB #adaptation #named
CHOP: Adaptive filter-based DRAM caching for CMP server platforms (XJ, NM, LZ, MU, RI, SM, DN, YS, RB), pp. 1–12.
HPCA-2009-KumarHM #manycore
Characterization of Direct Cache Access on multi-core systems and 10GbE (AK, RH, SM), pp. 341–352.
HPCA-2009-MadanZMUBIMN #3d #capacity #communication #configuration management #optimisation
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy (NM, LZ, NM, ANU, RB, RI, SM, DN), pp. 262–274.
HPCA-2004-MakineniI #architecture
Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor (SM, RRI), pp. 152–163.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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