Travelled to:1 × Germany
1 × India
6 × USA
Collaborated with:R.Balasubramonian N.P.Jouppi A.N.Udipi C.Xu D.Niu Y.Xie K.Ramani V.Venkatachalapathy N.Chatterjee A.Davis K.Chen S.Li J.H.Ahn J.B.Brockman D.H.Yoon J.Chang P.Ranganathan M.Erez T.Zhang S.Yu N.Madan L.Zhao R.Iyer S.Makineni D.Newell
Talks about:memori (4) architectur (3) dram (3) stack (2) level (2) read (2) microarchitectur (1) understand (1) reconfigur (1) hierarchi (1)
Person: Naveen Muralimanohar
DBLP: Muralimanohar:Naveen
Contributed to:
2015
2013
201220122011201020092005Wrote 8 papers:
- HPCA-2015-XuNMBZY0 #architecture #challenge #memory management
- Overcoming the challenges of crossbar resistive memory architectures (CX, DN, NM, RB, TZ, SY, YX), pp. 476–488.
- DAC-2013-XuNMJX #comprehension #design #memory management #multi #trade-off
- Understanding the trade-offs in multi-level cell ReRAM memory design (CX, DN, NM, NPJ, YX), p. 6.
- DATE-2012-ChenLMABJ #3d #architecture #in memory #memory management #modelling #named
- CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory (KC, SL, NM, JHA, JBB, NPJ), pp. 33–38.
- HPCA-2012-ChatterjeeMBDJ #staged
- Staged Reads: Mitigating the impact of DRAM writes on DRAM reads (NC, NM, RB, AD, NPJ), pp. 41–52.
- HPCA-2011-YoonMCRJE #fault #memory management #named
- FREE-p: Protecting non-volatile memory against both hard and soft errors (DHY, NM, JC, PR, NPJ, ME), pp. 466–477.
- HPCA-2010-UdipiMB #energy #network #scalability #towards
- Towards scalable, energy-efficient, bus-based on-chip networks (ANU, NM, RB), pp. 1–12.
- HPCA-2009-MadanZMUBIMN #3d #capacity #communication #configuration management #optimisation
- Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy (NM, LZ, NM, ANU, RB, RI, SM, DN), pp. 262–274.
- HPCA-2005-BalasubramonianMRV #architecture #performance
- Microarchitectural Wire Management for Performance and Power in Partitioned Architectures (RB, NM, KR, VV), pp. 28–39.