Travelled to:
2 × France
3 × Germany
4 × USA
Collaborated with:
A.L.Sangiovanni-Vincentelli R.K.Brayton A.Bernasconi V.Ciriani G.Trucco N.Yevtushenko R.Drechsler T.Kam A.Saldanha A.Mishchenko J.R.Jiang A.Petrenko G.D.Hachtel F.Somenzi A.Aziz S.Cheng S.A.Edwards S.P.Khatri Y.Kukimoto A.Pardo S.Qadeer R.K.Ranjan S.Sarwary T.R.Shiple G.Swamy
Talks about:
state (3) minim (3) languag (2) boolean (2) effici (2) fulli (2) equat (2) use (2) constraint (1) represent (1)
Person: Tiziano Villa
DBLP: Villa:Tiziano
Contributed to:
Wrote 9 papers:
- DATE-2013-BernasconiCTV #using
- Minimization of P-circuits using Boolean relations (AB, VC, GT, TV), pp. 996–1001.
- DATE-2009-BernasconiCTV #on the
- On decomposing Boolean functions via extended cofactoring (AB, VC, GT, TV), pp. 1464–1469.
- DATE-2006-BernasconiCDV #network #performance
- Efficient minimization of fully testable 2-SPP networks (AB, VC, RD, TV), pp. 1300–1305.
- DATE-2005-MishchenkoBJVY #equation #performance #using
- Efficient Solution of Language Equations Using Partitioned Representations (AM, RKB, JHRJ, TV, NY), pp. 418–423.
- DATE-2003-YevtushenkoVBPS #equation
- Equisolvability of Series vs. Controller’s Topology in Synchronous Language Equations (NY, TV, RKB, AP, ALSV), pp. 11154–11155.
- CAV-1996-BraytonHSSACEKKPQRSSSV #named #synthesis #verification
- VIS: A System for Verification and Synthesis (RKB, GDH, ALSV, FS, AA, STC, SAE, SPK, YK, AP, SQ, RKR, SS, TRS, GS, TV), pp. 428–432.
- DAC-1994-KamVBS #algorithm
- A Fully Implicit Algorithm for Exact State Minimization (TK, TV, RKB, ALSV), pp. 684–690.
- DAC-1991-SaldanhaVBS #constraints #encoding #framework
- A Framework for Satisfying Input and Output Encoding Constraints (AS, TV, RKB, ALSV), pp. 170–175.
- DAC-1989-VillaS #finite #implementation #logic #named #state machine
- NOVA: State Assignment of Finite State Machines for Optimal Two-level Logic Implementations (TV, ALSV), pp. 327–332.