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Travelled to:
1 × Belgium
1 × Canada
1 × France
1 × Germany
1 × Israel
1 × Italy
8 × USA
Collaborated with:
A.Aziz R.K.Brayton C.Pixley F.Balarin P.Aggarwal J.Baumgartner K.Sajid T.R.Shiple C.Yang M.J.Ciesielski P.Yalagandula R.K.Ranjan A.L.Sangiovanni-Vincentelli T.Heyman F.Somenzi T.Liu K.Sanwal R.L.Rudell A.Tripp F.Andersen A.Goel H.Zhou S.Cheng R.Hojati T.Kam S.C.Krishnan S.Tasiran H.Wang
Talks about:
verif (4) base (3) bdd (3) algorithm (2) sequenti (2) abstract (2) equival (2) circuit (2) system (2) formal (2)

Person: Vigyan Singhal

DBLP DBLP: Singhal:Vigyan

Contributed to:

CAV 20112011
CAV 20002000
DAC 20002000
DATE 20002000
CAV 19991999
DATE 19991999
CAV 19981998
DAC 19971997
CAV 19961996
CAV 19951995
DAC 19951995
CAV 19941994
DAC 19941994
ICALP 19941994

Wrote 15 papers:

CAV-2011-SinghalA #simulation #using #verification
Using Coverage to Deploy Formal Verification in a Simulation World (VS, PA), pp. 44–49.
CAV-2000-BaumgartnerTASA #abstraction #algorithm #design #verification
An Abstraction Algorithm for the Verification of Generalized C-Slow Designs (JB, AT, AA, VS, FA), pp. 5–19.
DAC-2000-YangCS #logic #named #optimisation
BDS: a BDD-based logic optimization system (CY, MJC, VS), pp. 92–97.
DATE-2000-YalagandulaAS #automation #generative
Automatic Lighthouse Generation for Directed State Space Search (PY, AA, VS), pp. 237–242.
CAV-1999-BaumgartnerHSA #abstraction #algorithm #model checking
Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists (JB, TH, VS, AA), pp. 72–83.
DATE-1999-RanjanSSB #using #verification
Using Combinational Verification for Sequential Circuits (RKR, VS, FS, RKB), pp. 138–144.
CAV-1998-GoelSZAS #formal method #similarity
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions (AG, KS, HZ, AA, VS), pp. 244–255.
DAC-1997-LiuSAS #black box #design #optimisation
Optimizing Designs Containing Black Boxes (THL, KS, AA, VS), pp. 113–116.
CAV-1996-AzizSSB #markov #verification
Verifying Continuous Time Markov Chains (AA, KS, VS, RKB), pp. 269–276.
CAV-1995-AzizSB #logic #probability
It Usually Works: The Temporal Logic of Stochastic Systems (AA, VS, FB), pp. 155–165.
The Validity of Retiming Sequential Circuits (VS, CP, RLR, RKB), pp. 316–321.
CAV-1994-AzizSS #composition #equivalence #model checking
Formula-Dependent Equivalence for Compositional CTL Model Checking (AA, TRS, VS), pp. 324–337.
CAV-1994-SinghalP #problem
The Verifiacation Problem for Safe Replaceability (VS, CP), pp. 311–323.
DAC-1994-AzizBCHKKRSSTWBS #named #verification
HSIS: A BDD-Based Environment for Formal Verification (AA, FB, STC, RH, TK, SCK, RKR, TRS, VS, ST, HYW, RKB, ALSV), pp. 454–459.
Equivalences for Fair Kripke Structures (AA, VS, FB, RKB, ALSV), pp. 364–375.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.