Travelled to:4 × France
4 × Germany
Collaborated with:A.J.v.d.Goor S.Hamdioui K.Bertels H.Mushtaq H.A.D.Nguyen G.Smaragdos C.Strydis G.Mueller J.Braun D.Richter C.Pham-Quoc J.Heisswolf S.Werner J.Becker
Talks about:fault (5) test (5) dram (4) memori (3) model (3) platform (2) acceler (2) stress (2) simul (2) cell (2)
Person: Zaid Al-Ars
DBLP: Al-Ars:Zaid
Contributed to:
20152013200620052004200320022001Wrote 9 papers:
- DATE-2015-NguyenASS #gpu #platform #simulation
- Accelerating complex brain-model simulations on GPU platforms (HADN, ZAA, GS, CS), pp. 974–979.
- DATE-2013-MushtaqAB #approach #fault tolerance #manycore #performance #platform
- Efficient software-based fault tolerance approach on multicore platforms (HM, ZAA, KB), pp. 921–926.
- DATE-2013-Pham-QuocHWABB #design #hardware #hybrid
- Hybrid interconnect design for heterogeneous hardware accelerators (CPQ, JH, SW, ZAA, JB, KB), pp. 843–846.
- DATE-2006-Al-ArsHG #fault #modelling #testing
- Space of DRAM fault models and corresponding testing (ZAA, SH, AJvdG), pp. 1252–1257.
- DATE-2005-Al-ArsHMG #analysis #fault #framework #generative #testing
- Framework for Fault Analysis and Test Generation in DRAMs (ZAA, SH, GM, AJvdG), pp. 1020–1021.
- DATE-v2-2004-Al-ArsG #fault #in memory #memory management #testing
- Soft Faults and the Importance of Stresses in Memory Testing (ZAA, AJvdG), pp. 1084–1091.
- DATE-2003-Al-ArsGBR #fault #optimisation #simulation #testing #using
- Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation (ZAA, AJvdG, JB, DR), pp. 10484–10489.
- DATE-2002-Al-ArsG #fault #in memory #memory management #modelling #testing
- Modeling Techniques and Tests for Partial Faults in Memory Devices (ZAA, AJvdG), pp. 89–93.
- DATE-2001-Al-ArsG #array #behaviour #embedded #memory management
- Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs (ZAA, AJvdG), pp. 496–503.