Travelled to:
1 × France
1 × Portugal
1 × United Kingdom
2 × Germany
3 × USA
Collaborated with:
N.Dershowitz A.Nadel J.Katz J.Moondanos G.Andersson P.Bjesse B.Cook C.H.Seger D.Kaiss F.Lu L.Wang K.Cheng R.Bruttomesso A.Cimatti A.Franzén A.Griggio A.Palti R.Sebastiani
Talks about:
solver (4) industri (2) problem (2) combin (2) model (2) check (2) bound (2) solv (2) sat (2) understand (1)
Person: Ziyad Hanna
DBLP: Hanna:Ziyad
Contributed to:
Wrote 9 papers:
- CAV-2007-BruttomessoCFGHNPS #industrial #lazy evaluation #problem #smt #verification
- A Lazy and Layered SMT(BV) Solver for Hard Industrial Verification Problems (RB, AC, AF, AG, ZH, AN, AP, RS), pp. 547–560.
- SAT-2007-DershowitzHN #comprehension #satisfiability #towards
- Towards a Better Understanding of the Functionality of a Conflict-Driven SAT Solver (ND, ZH, AN), pp. 287–293.
- SAT-2006-DershowitzHN #algorithm #satisfiability #scalability
- A Scalable Algorithm for Minimal Unsatisfiable Core Extraction (ND, ZH, AN), pp. 36–41.
- DATE-2005-KatzHD #bound #model checking
- Space-Efficient Bounded Model Checking (JK, ZH, ND), pp. 686–687.
- SAT-2005-DershowitzHK #bound #model checking
- Bounded Model Checking with QBF (ND, ZH, JK), pp. 408–414.
- SAT-2005-DershowitzHN #heuristic #satisfiability
- A Clause-Based Heuristic for SAT Solvers (ND, ZH, AN), pp. 46–60.
- DAC-2003-LuWCMH #case study #correlation #industrial
- A signal correlation guided ATPG solver and its applications for solving difficult industrial cases (FL, LCW, KTC, JM, ZH), pp. 436–441.
- DAC-2002-AnderssonBCH #approach #automation #design #problem #proving
- A proof engine approach to solving combinational design automation problems (GA, PB, BC, ZH), pp. 725–730.
- CAV-2001-MoondanosSHK #divide and conquer #equivalence #logic #named #verification
- CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination (JM, CJHS, ZH, DK), pp. 131–143.