BibSLEIGH — Amer

Travelled to:

3 × Germany
4 × France
4 × USA

Collaborated with:

M.Jézéquel A.A.Jerraya D.Lyonnard P.Murugappa H.Moussa O.Muller S.Yoo R.Al-Khayat P.Reddy F.Clermidy A.R.Jafri D.Karakolah N.Zergainoh V.M.Morales P.Horrein E.Hochapfel S.Vaton M.Rizk Y.Mohana Y.Atat S.Han M.Bonaciu S.Chae W.O.Cesário L.Gauthier G.Nicolescu Y.Paviot M.Diaz-Nava

Talks about:

multiprocessor (6) turbo (6) decod (6) architectur (4) flexibl (4) effici (4) design (4) applic (4) base (4) specif (3)

Person: Amer Baghdadi

DBLP: Baghdadi:Amer

Contributed to:

2014

2013

2011

2009

2008

2007

2006

2004

2002

2001

Wrote 13 papers:

DATE-2014-MoralesHBHV #energy #implementation #using: Energy-efficient FPGA implementation for binomial option pricing using OpenCL (VMM, PHH, AB, EH, SV), pp. 1–6.
DATE-2013-MurugappaBJ #multi #standard: Parameterized area-efficient multi-standard turbo decoder (PM, AB, MJ), pp. 109–114.
DATE-2013-RizkBJMA #case study #design: Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization (MR, AB, MJ, YM, YA), pp. 677–680.
DATE-2011-MurugappaABJ #architecture #flexibility #multi #throughput: A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding (PM, RAK, AB, MJ), pp. 228–233.
DATE-2011-ReddyCBJ #complexity #power management: A low complexity stopping criterion for reducing power consumption in turbo decoders (PR, FC, AB, MJ), pp. 649–654.
DATE-2009-JafriKBJ #flexibility #linear: ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications (ARJ, DK, AB, MJ), pp. 1620–1625.
DAC-2008-MoussaBJ #flexibility #multi #network: Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder (HM, AB, MJ), pp. 429–434.
DATE-2007-MoussaMBJ #communication #multi #network: Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding (HM, OM, AB, MJ), pp. 654–659.
DATE-2006-MullerBJ #design #multi: ASIP-based multiprocessor SoC design for simple and double binary turbo decoding (OM, AB, MJ), pp. 1330–1335.
DAC-2004-HanBBCJ #architecture #data transfer #distributed #flexibility #memory management #multi #performance #scalability: An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory (SIH, AB, MB, SIC, AAJ), pp. 250–255.
DAC-2002-CesarioBGLNPYJD #approach #component #design #manycore: Component-based design approach for multicore SoCs (WOC, AB, LG, DL, GN, YP, SY, AAJ, MDN), pp. 789–794.
DAC-2001-LyonnardYBJ #architecture #automation #generative #multi: Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip (DL, SY, AB, AAJ), pp. 518–523.
DATE-2001-BaghdadiLZJ #architecture #design #multi #performance: An efficient architecture model for systematic design of application-specific multiprocessor SoC (AB, DL, NEZ, AAJ), pp. 55–63.