BibSLEIGH — Niraj_K

Travelled to:

16 × USA
5 × France
7 × Germany

Collaborated with:

A.Raghunathan G.Lakshminarayana S.Ravi P.Gupta L.Peh L.Shang S.Dey I.Ghosh J.Luo B.P.Dave R.P.Dick M.Shoaib N.Verma W.Zhang L.Zhong T.K.Tan K.S.Khouri C.Lee P.Mishra N.Aaraj A.Muttreja A.Agrawal S.Bhatia D.Arora M.Zhang C.Li N.Agarwal L.Lingappan L.Yan S.Bhawmik T.Lee W.Wolf A.Kumar R.Zhang Y.Fei W.Wang K.Wakabayashi Y.Kim W.S.Lee V.Raghunathan N.R.Potlapally R.B.Lee M.Sankaradass S.T.Chakradhar

Talks about:

softwar (12) system (11) embed (11) synthesi (10) power (9) optim (9) architectur (8) energi (8) base (8) high (6)

Person: Niraj K. Jha

DBLP: Jha:Niraj_K=

Contributed to:

2015

2013

2012

2011

2010

2009

2007

2006

2005

2004

2003

2001

2000

1999

1998

1997

1996

1994

1993

Wrote 47 papers:

DAC-2015-KimLRJR: Vibration-based secure side channel for medical devices (YK, WSL, VR, NKJ, AR), p. 6.
DAC-2013-ZhangRJ #network #towards: Towards trustworthy medical devices and body area networks (MZ, AR, NKJ), p. 6.
DATE-2012-ShoaibJV #using: Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals (MS, NKJ, NV), pp. 437–442.
DAC-2011-LeeJ #framework #modelling #named #process: CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations (CYL, NKJ), pp. 866–871.
DAC-2011-ShoaibJV #algorithm #data-driven #energy #framework #monitoring #platform: A low-energy computation platform for data-driven biomedical monitoring algorithms (MS, NKJ, NV), pp. 591–596.
DATE-2010-MishraJ #optimisation #power management #synthesis #using: Low-power FinFET circuit synthesis using surface orientation optimization (PM, NKJ), pp. 311–314.
DATE-2009-LiRJ #architecture: An architecture for secure software defined radio (CL, AR, NKJ), pp. 448–453.
HPCA-2009-AgarwalPJ: In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects (NA, LSP, NKJ), pp. 67–78.
DAC-2007-ZhangSJ #architecture #configuration management #design #hybrid #named #optimisation: NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture (WZ, LS, NKJ), pp. 300–305.
DATE-2007-AarajRRJ #analysis #energy #execution #framework #platform: Energy and execution time analysis of a software-based trusted platform module (NA, AR, SR, NKJ), pp. 1128–1133.
DAC-2006-AroraRRSJC #architecture #mobile #multi #security: Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC (DA, AR, SR, MS, NKJ, STC), pp. 496–501.
DAC-2006-KumarSPJ #approach #coordination #named: HybDTM: a coordinated hardware-software approach for dynamic thermal management (AK, LS, LSP, NKJ), pp. 548–553.
DAC-2006-ZhangJS #architecture #configuration management #hybrid #named: NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture (WZ, NKJ, LS), pp. 711–716.
DATE-2006-GuptaJL #automaton #generative #quantum #testing: Test generation for combinational quantum cellular automata (QCA) circuits (PG, NKJ, LL), pp. 311–316.
DATE-DF-2006-AarajRRJ #architecture #authentication #embedded #performance: Architectures for efficient face authentication in embedded systems (NA, SR, AR, NKJ), pp. 1–6.
DATE-DF-2006-PotlapallyRRJL #encryption #framework #satisfiability: Satisfiability-based framework for enabling side-channel attacks on cryptographic software (NRP, AR, SR, NKJ, RBL), pp. 18–23.
DAC-2005-GuptaRRJ #authentication #embedded #performance: Efficient fingerprint-based user authentication for embedded systems (PG, SR, AR, NKJ), pp. 244–247.
DAC-2005-MuttrejaRRJ #embedded #energy #estimation #hybrid #simulation: Hybrid simulation for embedded software energy estimation (AM, AR, SR, NKJ), pp. 23–26.
DAC-2005-YanZJ #interactive #latency #scalability: User-perceived latency driven voltage scaling for interactive applications (LY, LZ, NKJ), pp. 624–627.
DATE-2005-AroraRRJ #embedded #monitoring #runtime: Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring (DA, SR, AR, NKJ), pp. 178–183.
DAC-2004-MuttrejaRRJ #automation #embedded #energy #megamodelling #performance: Automated energy/performance macromodeling of embedded software (AM, AR, SR, NKJ), pp. 99–102.
DATE-v2-2004-AgrawalJ #logic #synthesis: Synthesis of Reversible Logic (AA, NKJ), pp. 1384–1385.
DATE-v2-2004-GuptaJ #algorithm #architecture: An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology (PG, NKJ), pp. 974–979.
DATE-v2-2004-ZhangGZJ #logic #network #optimisation #synthesis: Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies (RZ, PG, LZ, NKJ), pp. 904–909.
DATE-2003-FeiRRJ #energy #estimation: Energy Estimation for Extensible Processors (YF, SR, AR, NKJ), pp. 10682–10687.
DATE-2003-LuoPJ #communication #distributed #embedded #realtime #scalability: Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems (JL, LSP, NKJ), pp. 11150–11151.
DATE-2003-TanRJ #approach #architecture #embedded #energy: Software Architectural Transformations: A New Approach to Low Energy Embedded Software (TKT, AR, NKJ), pp. 11046–11051.
HPCA-2003-ShangPJ #network #optimisation #scalability: Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks (LS, LSP, NKJ), pp. 91–102.
DAC-2001-LuoJ #distributed #embedded #realtime #scheduling: Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems (JL, NKJ), pp. 444–449.
DAC-2001-TanRLJ #energy #megamodelling: High-level Software Energy Macro-modeling (TKT, AR, GL, NKJ), pp. 605–610.
DAC-2001-WangRLJ #adaptation #design #energy #optimisation #performance: Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization (WW, AR, GL, NKJ), pp. 738–743.
DAC-2000-DickLRJ #analysis #embedded #operating system: Power analysis of embedded operating systems (RPD, GL, AR, NKJ), pp. 312–315.
DAC-1999-LakshminarayanaRKJD #optimisation #performance: Common-Case Computation: A High-Level Technique for Power and Performance Optimization (GL, AR, KSK, NKJ, SD), pp. 56–61.
DATE-1999-DickJ #multi #named #synthesis: MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis (RPD, NKJ), pp. 263–270.
DAC-1998-GhoshDJ #low cost #performance #testing: A Fast and Low Cost Testing Technique for Core-Based System-on-Chip (IG, SD, NKJ), pp. 542–547.
DAC-1998-GhoshJB #analysis #testing: A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis (IG, NKJ, SB), pp. 554–559.
DAC-1998-LakshminarayanaJ #behaviour #control flow #framework #named #optimisation #throughput: FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions (GL, NKJ), pp. 102–107.
DAC-1998-LakshminarayanaJ98a #behaviour #power management #synthesis: Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions (GL, NKJ), pp. 439–444.
DAC-1998-LakshminarayanaRJ #behaviour #control flow #execution #scheduling: Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions (GL, AR, NKJ), pp. 108–113.
DATE-1998-DaveJ #architecture #concurrent #embedded #named #realtime #specification: CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures (BPD, NKJ), pp. 118–124.
DATE-1998-KhouriLJ #control flow #named #power management #synthesis: IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits (KSK, GL, NKJ), pp. 848–854.
DAC-1997-DaveLJ #embedded #named: COSYN: Hardware-Software Co-Synthesis of Embedded Systems (BPD, GL, NKJ), pp. 703–708.
DAC-1997-GhoshRJ #design #generative #testing: Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs (IG, AR, NKJ), pp. 534–539.
DAC-1997-RaghunathanDJW #control flow #design #power management: Power Management Techniques for Control-Flow Intensive Designs (AR, SD, NKJ, KW), pp. 429–434.
DAC-1996-RaghunathanDJ #analysis #reduction: Glitch Analysis and Reduction in Register Transfer Level (AR, SD, NKJ), pp. 331–336.
EDAC-1994-BhatiaJ #behaviour #named #synthesis #testing: Genesis: A Behavioral Synthesis System for Hierarchical Testability (SB, NKJ), pp. 272–276.
DAC-1993-LeeJW #behaviour #synthesis: Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments (TCL, NKJ, WW), pp. 292–297.