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Travelled to:
11 × USA
7 × France
9 × Germany
Collaborated with:
K.Richter M.Jersak P.Axer M.Negrean J.Rox R.Henia S.Quinton F.Wolf D.Thiele J.Staschulat S.Schliecker J.Diemer S.Heithecker M.Neukirchner H.Sahlbach S.Whitty M.Beckert A.Hamann E.A.Rambo D.Ziegenbein S.Stein A.A.Jerraya J.Henkel D.Herrmann W.Putzke-Röming J.Teich A.d.C.Lucas S.Klawitter M.Sebastian M.Hanke P.Giusto S.M.Petters D.Bertrand P.M.Yomsi H.Schrom R.Racu A.Schulze K.Tindell H.Kopetz C.Haubelt A.Tschiene L.Ahrendts T.Michaels B.Hurlburt H.Sarnowski M.Bekooij S.Chakraborty E.Frank R.Wilhelm A.L.Sangiovanni-Vincentelli M.D.Natale J.Kruse C.Thomsen T.Volling T.Spengler L.Thiele T.T.Bone J.Hennig J.Braam Z.Jiang P.Rüffer H.Rückert G.Wischermann K.Gebel R.Fach W.Huther S.Eichner G.Scheller
Talks about:
analysi (27) time (22) system (17) perform (10) design (9) automot (8) real (8) softwar (7) schedul (7) network (7)

Person: Rolf Ernst

DBLP DBLP: Ernst:Rolf

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
DATE 20122012
DATE 20102010
DATE 20092009
DATE 20082008
DAC 20072007
DATE 20072007
DATE 20062006
DATE Designers’ Forum 20062006
DAC 20052005
DATE 20052005
LCTES 20052005
DATE v2 20042004
DAC 20032003
DATE 20032003
DAC 20022002
DATE 20022002
LCTES/OM 20012001
DAC 19991999
DATE 19991999
DAC 19971997
ED&TC 19971997

Wrote 53 papers:

DAC-2015-BeckertE #design #independence #realtime
Designing time partitions for real-time hypervisor with sufficient temporal independence (MB, RE), p. 6.
DAC-2015-ThieleAE #analysis #scheduling
Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling (DT, PA, RE), p. 6.
DATE-2015-RamboE #analysis #communication #worst-case
Worst-case communication time analysis of networks-on-chip with shared virtual channels (EAR, RE), pp. 537–542.
DAC-2014-AxerTED #bound #network #performance
Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks (PA, DT, RE, JD), p. 6.
DAC-2014-BeckertNEP #independence #realtime
Sufficient Temporal Independence and Improved Interrupt Latencies in a Real-Time Hypervisor (MB, MN, RE, SMP), p. 6.
DAC-2014-QuintonBHNNE #analysis #design #network
Typical Worst Case Response-Time Analysis and its Use in Automotive Network Design (SQ, TTB, JH, MN, MN, RE), p. 6.
DATE-2014-RamboTDAE #analysis #realtime
Failure analysis of a network-on-chip for real-time mixed-critical systems (EAR, AT, JD, LA, RE), pp. 1–4.
DAC-2013-AxerE #fault #probability #scheduling
Stochastic response-time guarantee for non-preemptive, fixed-priority scheduling under errors (PA, RE), p. 7.
DATE-2013-NegreanKE #analysis #manycore
Timing analysis of multi-mode applications on AUTOSAR conform multi-core systems (MN, SK, RE), pp. 302–307.
DATE-2013-NeukirchnerQMAE #analysis #realtime
Sensitivity analysis for arbitrary activation patterns in real-time systems (MN, SQ, TM, PA, RE), pp. 135–140.
DATE-2013-QuintonNE #analysis #formal method #realtime
Formal analysis of sporadic bursts in real-time systems (SQ, MN, RE), pp. 767–772.
DATE-2012-AxerSE #bound #probability
Probabilistic response time bound for CAN messages with arbitrary deadlines (PA, MS, RE), pp. 1114–1117.
DATE-2012-QuintonEBY #analysis #challenge #probability #roadmap
Challenges and new trends in probabilistic timing analysis (SQ, RE, DB, PMY), pp. 810–815.
DATE-2012-QuintonHE #analysis #formal method #realtime
Formal analysis of sporadic overload in real-time systems (SQ, MH, RE), pp. 515–520.
DATE-2012-RoxEG #analysis #design #network #using
Using timing analysis for the design of future switched based Ethernet automotive networks (JR, RE, PG), pp. 57–62.
DATE-2012-SahlbachWE
A high-performance dense block matching solution for automotive 6D-vision (HS, SW, RE), pp. 268–271.
DATE-2012-ThieleE #analysis #data flow #graph #optimisation #performance
Optimizing performance analysis for synchronous dataflow graphs with shared resources (DT, RE), pp. 635–640.
DATE-2010-NeukirchnerSSE #self
A software update service with self-protection capabilities (MN, SS, HS, RE), pp. 903–908.
DATE-2010-RoxE #correlation
Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasks (JR, RE), pp. 226–231.
DATE-2010-SchlieckerNE #analysis #bound #multi #performance
Bounding the shared resource load for the performance analysis of multiprocessor systems (SS, MN, RE), pp. 759–764.
DATE-2010-WhittySHEP #architecture #configuration management #memory management #performance
Application-specific memory performance of a heterogeneous reconfigurable architecture (SW, HS, BH, RE, WPR), pp. 387–392.
DATE-2009-DiemerE #quality
A link arbitration scheme for quality of service in a latency-optimized network-on-chip (JD, RE), pp. 574–577.
DATE-2009-NegreanSE #analysis #multi
Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources (MN, SS, RE), pp. 524–529.
DATE-2009-RichterJE #framework #learning #verification
Learning early-stage platform dimensioning from late-stage timing verification (KR, MJ, RE), pp. 851–857.
DATE-2009-WhittySEP #algorithm #architecture #configuration management
Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture (SW, HS, RE, WPR), pp. 27–32.
DATE-2008-ErnstJSBC #analysis #formal method #optimisation #performance
Formal Methods in System and MpSoC Performance Analysis and Optimisation (RE, MJ, HS, MB, SC).
DATE-2008-FrankWESN #analysis #architecture #design #evaluation #standard #tool support
Methods, Tools and Standards for the Analysis, Evaluation and Design of Modern Automotive Architectures (EF, RW, RE, ALSV, MDN), pp. 659–663.
DATE-2008-RoxE #modelling
Modeling Event Stream Hierarchies with Hierarchical Event Models (JR, RE), pp. 492–497.
DAC-2007-LucasHE #library #named #realtime
FlexWAFE — A High-end Real-Time Stream Processing Library for FPGAs (AdCL, SH, RE), pp. 916–921.
DAC-2007-RacuHER #integration
Automotive Software Integration (RR, AH, RE, KR), pp. 545–550.
DATE-2007-SchlieckerSE #analysis #composition #data flow #graph #integration #performance
Performance analysis of complex systems by integration of dataflow graphs and compositional performance analysis (SS, SS, RE), pp. 273–278.
DATE-2006-HeniaE #multi #using
Improved offset-analysis using multiple timing-references (RH, RE), pp. 450–455.
DATE-2006-LucasHRERWGFHES #configuration management #framework #platform #realtime
A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications (AdCL, SH, PR, RE, HR, GW, KG, RF, WH, SE, GS), pp. 194–199.
DATE-DF-2006-RichterE #challenge #how #integration #network
How OEMs and suppliers can face the network integration challenges (KR, RE), pp. 183–188.
DAC-2005-HeitheckerE #requirements
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements (SH, RE), pp. 575–578.
DATE-2005-HamannE #optimisation #search-based
TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques (AH, RE), pp. 312–317.
DATE-2005-HeniaE #analysis #distributed #scheduling
Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies (RH, RE), pp. 480–485.
DATE-2005-KruseTEVS #contract #design #distributed #embedded #flexibility #process
Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes (JK, CT, RE, TV, TS), pp. 938–943.
DATE-2005-StaschulatESW #analysis #performance
Context Sensitive Performance Analysis of Automotive Applications (JS, RE, AS, FW), pp. 165–170.
LCTES-2005-StaschulatE #analysis #precise #scalability #scheduling
Scalable precision cache analysis for preemptive scheduling (JS, RE), pp. 157–165.
DATE-v2-2004-JersakHE #analysis #design #embedded #performance
Context-Aware Performance Analysis for Efficient Embedded System Design (MJ, RH, RE), pp. 1046–1051.
DAC-2003-JersakE #analysis #dependence #multi #scheduling
Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals (MJ, RE), pp. 454–459.
DATE-2003-JersakREBJW #formal method #integration
Formal Methods for Integration of Automotive Software (MJ, KR, RE, JCB, ZYJ, FW), pp. 20045–20050.
DATE-2003-TindellKWE #development
Safe Automotive Software Development (KT, HK, FW, RE), pp. 10616–10623.
DAC-2002-RichterZJE #analysis #composition #design #framework #platform #scheduling
Model composition for scheduling analysis in platform design (KR, DZ, MJ, RE), pp. 287–292.
DAC-2002-WolfSE #analysis #formal method
Associative caches in formal software timing analysis (FW, JS, RE), pp. 622–627.
DATE-2002-HaubeltTRE #design #flexibility
System Design for Flexibility (CH, JT, KR, RE), pp. 854–861.
DATE-2002-RichterE #analysis #interface
Event Model Interfaces for Heterogeneous System Analysis (KR, RE), pp. 506–513.
LCTES-OM-2001-ZiegenbeinWRJE #analysis #process
Interval-Based Analysis of Software Processes (DZ, FW, KR, MJ, RE), pp. 94–101.
DAC-1999-RichterZETT #embedded #optimisation #representation #synthesis
Representation of Function Variants for Embedded System Optimization and Synthesis (KR, DZ, RE, LT, JT), pp. 517–522.
DATE-1999-JerrayaE #design #multi
Multi-Language System Design (AAJ, RE), p. 696–?.
DAC-1997-HenkelE #hardware #using
A Hardware/Software Partitioner Using a Dynamically Determined Granularity (JH, RE), pp. 691–696.
EDTC-1997-HerrmannE #synthesis
Register synthesis for speculative computation (DH, RE), pp. 463–467.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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