Person: Claudio Passerone

DBLP: Passerone:Claudio

Contributed to:

2005

2004

2003

2002

2001

2000

1999

1998

1997

1995

Wrote 10 papers:

DATE-2005-LavagnoPSW #design #slicing

A Time Slice Based Scheduler Model for System Level Design (LL, CP, VS, YW), pp. 378–383.

DATE-v2-2004-RosaPGL #configuration management #framework #implementation

Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform (ALR, CP, FG, LL), pp. 1218–1223.

DATE-2003-RosaLP #configuration management #design #hardware

Hardware/Software Design Space Exploration for a Reconfigurable Processor (ALR, LL, CP), pp. 10570–10575.

DATE-2002-ArrigoniDPLW #scheduling

False Path Elimination in Quasi-Static Scheduling (GA, LD, CP, LL, YW), pp. 964–970.

DATE-2001-PasseroneWL #generative #graph #scheduling

Generation of minimal size code for scheduling graphs (CP, YW, LL), pp. 668–673.

DAC-2000-CortadellaKLMMPWS #embedded #generative #scheduling

Task generation and compile-time scheduling for mixed data-control embedded software (JC, AK, LL, MM, SM, CP, YW, ALSV), pp. 489–494.

DATE-1999-CabodiCPQ #simulation

Computing Timed Transition Relations for Sequential Cycle-Based Simulation (GC, PC, CP, SQ), pp. 8–12.

DAC-1998-CuattoPLJDSS #case study #design #embedded

A Case Study in Embedded System Design: An Engine Control Unit (TC, CP, LL, AJ, AD, CS, ALSV), pp. 804–807.

DAC-1997-PasseroneLCS #analysis #hardware #performance #prototype #trade-off

Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis (CP, LL, MC, ALSV), pp. 389–394.

PDP-1995-GregorettiP #architecture #parallel #testing #using

Using a massively parallel architecture for integrated circuits testing (FG, CP), pp. 332–338.