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Travelled to:
2 × Germany
4 × France
8 × USA
Collaborated with:
Y.Watanabe L.Lavagno M.Kishinevsky J.Cortadella K.Lwin A.Yakovlev M.Meyer M.Marek-Sadowska Y.Ran A.L.Sangiovanni-Vincentelli A.Davare B.Hu A.G.Lomeña M.L.López-Vallejo C.P.Sotiriou B.Lin P.Vanbekbergen A.Taubin V.Varshavsky E.E.Pissaloux D.Chai K.H.Tseng M.Massot S.Moral C.Passerone
Talks about:
asynchron (6) synthesi (6) circuit (5) high (4) synchron (3) approach (3) analysi (3) speed (3) level (3) base (3)

Person: Alex Kondratyev

DBLP DBLP: Kondratyev:Alex

Contributed to:

DATE 20132013
DATE 20122012
DATE 20112011
DAC 20042004
DATE v2 20042004
DAC 20032003
DATE 20032003
DAC 20022002
DAC 20002000
DAC 19991999
DAC 19981998
ED&TC 19971997
DAC 19961996
DAC 19941994
PDP 19941994

Wrote 17 papers:

DATE-2013-KondratyevLMW #evaluation #synthesis
Share with care: a quantitative evaluation of sharing approaches in high-level synthesis (AK, LL, MM, YW), pp. 1547–1552.
DATE-2012-KondratyevLMW #synthesis #trade-off
Exploiting area/delay tradeoffs in high-level synthesis (AK, LL, MM, YW), pp. 1024–1029.
DATE-2011-KondratyevLMW #pipes and filters #synthesis
Realistic performance-constrained pipelining in high-level synthesis (AK, LL, MM, YW), pp. 1382–1387.
DAC-2004-DavareLKS #implementation #performance #specification
The best of both worlds: the efficient asynchronous implementation of synchronous specifications (AD, KL, AK, ALSV), pp. 588–591.
DATE-v2-2004-CortadellaKLLS #approach #automation
From Synchronous to Asynchronous: An Automatic Approach (JC, AK, LL, KL, CPS), pp. 1368–1369.
DATE-v2-2004-RanKWM #analysis
Eliminating False Positives in Crosstalk Noise Analysis (YR, AK, YW, MMS), pp. 1192–1197.
DAC-2003-ChaiKRTWM #analysis
Temporofunctional crosstalk noise analysis (DC, AK, YR, KHT, YW, MMS), pp. 860–863.
DAC-2003-HuWKM #library
Gain-based technology mapping for discrete-size cell libraries (BH, YW, AK, MMS), pp. 574–579.
DATE-2003-LomenaLWK #approach #explosion #performance #scheduling
An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling (AGL, MLLV, YW, AK), pp. 10428–10435.
DAC-2002-KondratyevL #design #tool support
Design of asynchronous circuits by synchronous CAD tools (AK, KL), pp. 411–414.
DAC-2000-CortadellaKLMMPWS #embedded #generative #scheduling
Task generation and compile-time scheduling for mixed data-control embedded software (JC, AK, LL, MM, SM, CP, YW, ALSV), pp. 489–494.
DAC-1999-KondratyevCKLY #automation #optimisation #synthesis
Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems (AK, JC, MK, LL, AY), pp. 110–115.
DAC-1998-KishinevskyCK #analysis #interface #specification #synthesis
Asynchronous Interface Specification, Analysis and Synthesis (MK, JC, AK), pp. 2–7.
EDTC-1997-CortadellaKKLY #composition #independence
Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis (JC, MK, AK, LL, AY), pp. 98–105.
DAC-1996-CortadellaKKLY #encoding #synthesis #tool support
Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis (JC, MK, AK, LL, AY), pp. 63–66.
DAC-1994-KondratyevKLVY #implementation #independence
Basic Gate Implementation of Speed-Independent Circuits (AK, MK, BL, PV, AY), pp. 56–62.
PDP-1994-KondratyevTVKP #behaviour #diagrams #parallel
Change Diagram : A behavioural model for very speed VLSI circuit/highly parallel systems (AK, AT, VV, MK, EEP), pp. 220–226.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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