Travelled to:
2 × United Kingdom
3 × Germany
4 × France
Collaborated with:
Z.Peng A.Larsson P.Eles V.Singh M.Väyrynen F.G.Zadegan U.Ingelsson G.Carlsson P.Subramanyan K.K.Saluja M.Amirijoo D.Karlsson X.Gu K.Kuchcinski K.Chakrabarty T.Dubois E.J.Marinissen M.Azimane P.Wielage C.Wouters
Talks about:
test (7) optim (3) chip (3) architectur (2) techniqu (2) compress (2) analysi (2) system (2) integr (2) execut (2)
Person: Erik Larsson
DBLP: Larsson:Erik
Contributed to:
Wrote 10 papers:
- DATE-2011-ZadeganICL #automation #design
- Design automation for IEEE P1687 (FGZ, UI, GC, EL), pp. 1412–1417.
- DATE-2010-SubramanyanSSL #execution #fault tolerance #multi #performance
- Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors (PS, VS, KKS, EL), pp. 1572–1577.
- DATE-2009-VayrynenSL #execution #fault tolerance #multi #optimisation
- Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips (MV, VS, EL), pp. 484–489.
- DATE-2008-LarssonLCEP #architecture #optimisation #scheduling
- Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns (AL, EL, KC, PE, ZP), pp. 188–193.
- DATE-2007-DuboisMAWLW #analysis #embedded #quality
- Test quality analysis and improvement for an embedded asynchronous FIFO (TD, EJM, MA, PW, EL, CW), pp. 859–864.
- DATE-2007-LarssonLEP #integration #testing
- Optimized integration of test compression and sharing for SOC testing (AL, EL, PE, ZP), pp. 207–212.
- ITiCSE-2007-LarssonAKE #evaluation #question #what
- What impacts course evaluation? (EL, MA, DK, PE), p. 333.
- ITiCSE-2004-LarssonL #architecture #student
- Student-oriented examination in a computer architecture course (EL, AL), p. 245.
- DATE-2001-LarssonP #framework
- An integrated system-on-chip test framework (EL, ZP), pp. 138–144.
- EDTC-1997-GuLKP #analysis #testing
- A controller testability analysis and enhancement technique (XG, EL, KK, ZP), pp. 153–157.