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Travelled to:
1 × France
1 × Germany
1 × India
1 × Mexico
6 × USA
Collaborated with:
D.H.Woo T.Suh M.Smelyanskiy C.S.Ballapuram M.Ekpanyapong S.K.Lim A.Sharif D.Kim D.M.Blough N.H.Seong D.L.Lewis S.A.Mahlke E.S.Davidson C.J.Newburn G.S.Tyson J.R.Minz T.Watewai W.Shi J.B.Fryman G.Gu Y.Zhang J.Yang M.B.Healy M.Vittes G.H.Loh
Talks about:
microarchitectur (3) architectur (3) stack (3) multiprocessor (2) heterogen (2) floorplan (2) support (2) exploit (2) memori (2) reduc (2)

Person: Hsien-Hsin S. Lee

DBLP DBLP: Lee:Hsien=Hsin_S=

Contributed to:

ASPLOS 20102010
HPCA 20102010
ASPLOS 20082008
DATE 20062006
HPCA 20062006
DAC 20052005
DAC 20042004
DATE v2 20042004
CGO 20032003
HPCA 20012001

Wrote 10 papers:

ASPLOS-2010-WooL #gpu #named #programmable #using
COMPASS: a programmable data prefetcher using idle GPU shaders (DHW, HHSL), pp. 297–310.
HPCA-2010-WooSLL #3d #architecture #memory management
An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth (DHW, NHS, DLL, HHSL), pp. 1–12.
ASPLOS-2008-BallapuramSL #behaviour #multi #semantics
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors (CSB, AS, HHSL), pp. 60–69.
DATE-2006-HealyVEBLLL #architecture #performance #trade-off
Microarchitectural floorplanning under performance and thermal tradeoff (MBH, MV, ME, CSB, SKL, HHSL, GHL), pp. 1288–1293.
HPCA-2006-ShiFGLZY #architecture #in memory #memory management #named #security
InfoShield: a security architecture for protecting information usage in memory (WS, JBF, GG, HHSL, YZ, JY), pp. 222–231.
DAC-2005-SuhKL #architecture
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs (TS, DK, HHSL), pp. 553–558.
DAC-2004-EkpanyapongMWLL #architecture #design
Profile-guided microarchitectural floorplanning for deep submicron processor design (ME, JRM, TW, HHSL, SKL), pp. 634–639.
DATE-v2-2004-SuhBL #multi
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems (TS, DMB, HHSL), pp. 1150–1157.
CGO-2003-SmelyanskiyMDL #constraints #scheduling
Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints (MS, SAM, ESD, HHSL), pp. 169–178.
HPCA-2001-LeeSNT #architecture #stack
Stack Value File: Custom Microarchitecture for the Stack (HHSL, MS, CJN, GST), pp. 5–14.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.