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Travelled to:
1 × Germany
6 × USA
Collaborated with:
L.He H.Yu S.Chang H.Chen J.Xiong Y.Chen K.Lai J.Cong G.Luo B.Xiao V.Zolotov C.Visweswariah P.Mesa C.Lung Y.Su S.Huang T.Wang W.Wen M.Lee W.Hon F.Gong D.Kim J.Ren Y.Liu S.Hu J.Wu Y.Jin Y.Hu X.Li C.Zhang P.Deng H.Geng J.Liu Q.Zhu
Talks about:
yield (3) base (3) memcomput (2) structur (2) circuit (2) simul (2) awar (2) cyberattack (1) triangular (1) constraint (1)

Person: Yiyu Shi


Contributed to:

DAC 20152015
DAC 20142014
DATE 20142014
DAC 20112011
DAC 20102010
DAC 20092009
DAC 20062006

Wrote 12 papers:

DAC-2015-LiuHWSJHL #assessment #detection #smarttech
Impact assessment of net metering on smart home cyberattack detection (YL, SH, JW, YS, YJ, YH, XL), p. 6.
DAC-2014-ChenWLWSC #design #monitoring #scalability
Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs (YGC, TW, KYL, WYW, YS, SCC), p. 6.
DATE-2014-ChenLLSHC #3d
Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits (YGC, KYL, MCL, YS, WKH, SCC), pp. 1–4.
DATE-2014-ShiC #named
Memcomputing: The cape of good hope: [Extended special session description] (YS, HMC), pp. 1–3.
DATE-2014-ZhangDGLZXS #framework #named #simulation
MSim: A general cycle accurate simulation platform for memcomputing studies (CZ, PD, HG, JL, QZ, JX, YS), pp. 1–5.
DAC-2011-CongLS #3d
Thermal-aware cell and through-silicon-via co-placement for 3D ICs (JC, GL, YS), pp. 670–675.
DAC-2011-LungSHSC #3d #fault tolerance #network
Fault-tolerant 3D clock network (CLL, YSS, SHH, YS, SCC), pp. 645–651.
DAC-2010-GongYSKRH #constraints #estimation #named #parametricity #performance
QuickYield: an efficient global-search based parametric yield estimation with performance constraints (FG, HY, YS, DK, JR, LH), pp. 392–397.
DAC-2010-XiaoSH #algorithm
A universal state-of-charge algorithm for batteries (BX, YS, LH), pp. 687–692.
DAC-2009-XiongSZV #multi #process #statistics
Statistical multilayer process space coverage for at-speed test (JX, YS, VZ, CV), pp. 340–345.
DAC-2006-ShiMYH #simulation
Circuit simulation based obstacle-aware Steiner routing (YS, PM, HY, LH), pp. 385–388.
DAC-2006-YuSH #analysis #grid #order #performance #power management #reduction
Fast analysis of structured power grid by triangularization based structure preserving model order reduction (HY, YS, LH), pp. 205–210.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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