BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
3 × France
4 × Germany
Collaborated with:
L.Benini F.Angiolini M.R.Kakoee C.Weis N.Wehn E.Azarkhish D.Rossi A.Rahimi
Talks about:
share (3) dram (3) interconnect (2) processor (2) platform (2) interfac (2) network (2) cluster (2) memori (2) effici (2)

Person: Igor Loi


Contributed to:

DATE 20152015
DATE 20142014
DATE 20122012
DATE 20112011
DATE 20102010
DATE 20092009
DATE 20082008

Wrote 9 papers:

DATE-2015-AzarkhishRLB #memory management #performance
High performance AXI-4.0 based interconnect for extensible smart memory cubes (EA, DR, IL, LB), pp. 1317–1322.
DATE-2014-LoiB #multi
A multi banked — Multi ported — Non blocking shared L2 cache for MPSoC platforms (IL, LB), pp. 1–6.
DATE-2012-KakoeeLB #architecture #clustering #communication #latency
A resilient architecture for low latency communication in shared-L1 processor clusters (MRK, IL, LB), pp. 887–892.
DATE-2012-WeisLBW #3d #energy #performance
An energy efficient DRAM subsystem for 3D integrated SoCs (CW, IL, LB, NW), pp. 1138–1141.
DATE-2011-RahimiLKB #clustering #network
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters (AR, IL, MRK, LB), pp. 491–496.
DATE-2011-WeisWLB #3d #design
Design space exploration for 3D-stacked DRAMs (CW, NW, IL, LB), pp. 389–394.
DATE-2010-LoiB #3d #distributed #framework #interface #manycore #memory management #performance
An efficient distributed memory interface for many-core platform with 3D stacked DRAM (IL, LB), pp. 99–104.
DATE-2009-LoiAB #configuration management #interface #network #synthesis
Synthesis of low-overhead configurable source routing tables for network interfaces (IL, FA, LB), pp. 262–267.
DATE-2008-LoiAB #3d
Developing Mesochronous Synchronizers to Enable 3D NoCs (IL, FA, LB), pp. 1414–1419.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.