Travelled to:2 × USA
Collaborated with:C.Kyung S.Bae Y.Hwang C.Park H.Choi W.Yang H.Oh I.Park
Talks about:methodolog (2) design (2) base (2) microprocessor (1) interconnect (1) submicron (1) floorplan (1) distribut (1) datapath (1) complex (1)
Person: Joon-Seo Yim
DBLP: Yim:Joon=Seo
Contributed to:
19991997Wrote 3 papers:
- DAC-1999-YimBK
- A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs (JSY, SOB, CMK), pp. 766–771.
- DAC-1999-YimK #design
- Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design (JSY, CMK), pp. 485–490.
- DAC-1997-YimHPCYOPK #design #verification
- A C-Based RTL Design Verification Methodology for Complex Microprocessor (JSY, YHH, CJP, HC, WSY, HSO, ICP, CMK), pp. 83–88.