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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
2 × USA
Collaborated with:
C.Kyung S.Bae Y.Hwang C.Park H.Choi W.Yang H.Oh I.Park
Talks about:
methodolog (2) design (2) base (2) microprocessor (1) interconnect (1) submicron (1) floorplan (1) distribut (1) datapath (1) complex (1)

Person: Joon-Seo Yim

DBLP DBLP: Yim:Joon=Seo

Contributed to:

DAC 19991999
DAC 19971997

Wrote 3 papers:

A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs (JSY, SOB, CMK), pp. 766–771.
DAC-1999-YimK #design
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design (JSY, CMK), pp. 485–490.
DAC-1997-YimHPCYOPK #design #verification
A C-Based RTL Design Verification Methodology for Complex Microprocessor (JSY, YHH, CJP, HC, WSY, HSO, ICP, CMK), pp. 83–88.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.