BibSLEIGH — Chong-Min

Travelled to:

1 × Germany
3 × France
5 × USA

Collaborated with:

I.Park Y.Kwon J.Yim H.Choi Y.Kim S.Lee J.H.Yi W.Yang J.Kim S.Yoo S.Bae Y.Chang J.Lee S.H.Hwang J.Lee M.Chung K.Ahn S.Lee N.Kim S.Lee Y.Hwang C.Park H.Oh J.Yang B.Kim S.Nam J.Cho S.Seo C.Ryu D.Lee J.Kim H.Yoon J.Kim K.Lee C.Hwang I.Kim J.S.Kim K.Park K.H.Park Y.H.Lee

Talks about:

function (4) design (3) base (3) microprocessor (2) methodolog (2) distribut (2) synthesi (2) softwar (2) hardwar (2) coverag (2)

Person: Chong-Min Kyung

DBLP: Kyung:Chong=Min

Contributed to:

2009

2005

2004

1999

1998

1997

1991

Wrote 14 papers:

DATE-2009-KimYK #online #runtime #scalability: Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling (JK, SY, CMK), pp. 417–422.
DATE-2005-LeeCALK #hardware #predict #transaction: A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation (JGL, MKC, KYA, SHL, CMK), pp. 384–389.
DAC-2004-KimYKK #functional #hardware #performance #simulation: Communication-efficient hardware acceleration for fast functional simulation (YIK, WSY, YSK, CMK), pp. 293–298.
DAC-2004-KwonKK #functional #graph #metric #synthesis: Systematic functional coverage metric synthesis from hierarchical temporal event relation graph (YSK, YIK, CMK), pp. 45–48.
DATE-v1-2004-KwonK #functional #generative #graph #metric: Functional Coverage Metric Generation from Temporal Event Relation Graph (YSK, CMK), pp. 670–671.
DAC-1999-ChangLPK #using #verification: Verification of a Microprocessor Using Real World Applications (YSC, SL, ICP, CMK), pp. 181–184.
DAC-1999-ChoiYLPK #design #embedded: Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software (HC, JHY, JYL, ICP, CMK), pp. 939–944.
DAC-1999-YimBK: A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs (JSY, SOB, CMK), pp. 766–771.
DAC-1999-YimK #design: Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design (JSY, CMK), pp. 485–490.
DAC-1998-KimCLLPK #functional #modelling: Virtual Chip: Making Functional Models Work on Real Target Systems (NK, HC, SL, SL, ICP, CMK), pp. 170–173.
DAC-1998-YangKNCSRKLLKYKLHKKPPLHPK #development #named: MetaCore: An Application Specific DSP Development System (JHY, BWK, SJN, JHC, SWS, CHR, YSK, DHL, JYL, JSK, HDY, JYK, KML, CSH, IHK, JSK, KIP, KHP, YHL, SHH, ICP, CMK), pp. 800–803.
DATE-1998-YiCPHK #behaviour #multi #synthesis: Multiple Behavior Module Synthesis Based on Selective Groupings (JHY, HC, ICP, SHH, CMK), pp. 384–388.
DAC-1997-YimHPCYOPK #design #verification: A C-Based RTL Design Verification Methodology for Complex Microprocessor (JSY, YHH, CJP, HC, WSY, HSO, ICP, CMK), pp. 83–88.
DAC-1991-ParkK #automation #performance #scheduling: Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis (ICP, CMK), pp. 680–685.