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Travelled to:
1 × France
7 × USA
Collaborated with:
C.Kyung H.Kang J.Lee H.Choi S.Lee J.H.Yi Y.Chang S.H.Hwang N.Kim S.Lee J.Yim Y.Hwang C.Park W.Yang H.Oh J.Yang B.Kim S.Nam J.Cho S.Seo C.Ryu Y.Kwon D.Lee J.Kim H.Yoon J.Kim K.Lee C.Hwang I.Kim J.S.Kim K.Park K.H.Park Y.H.Lee
Talks about:
base (4) design (3) microprocessor (2) synthesi (2) softwar (2) system (2) applic (2) verif (2) model (2) embed (2)

Person: In-Cheol Park

DBLP DBLP: Park:In=Cheol

Contributed to:

DAC 20032003
DAC 20022002
DAC 20012001
DAC 19991999
DAC 19981998
DATE 19981998
DAC 19971997
DAC 19911991

Wrote 10 papers:

DAC-2003-KangP #bound #model checking #satisfiability
SAT-based unbounded symbolic model checking (HJK, ICP), pp. 840–843.
DAC-2002-LeeP #analysis #design #embedded #performance #simulation
Timed compiled-code simulation of embedded software for performance analysis of SOC design (JYL, ICP), pp. 293–298.
DAC-2001-ParkK #representation #synthesis
Digital Filter Synthesis Based on Minimal Signed Digit Representation (ICP, HJK), pp. 468–473.
DAC-1999-ChangLPK #using #verification
Verification of a Microprocessor Using Real World Applications (YSC, SL, ICP, CMK), pp. 181–184.
DAC-1999-ChoiYLPK #design #embedded
Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software (HC, JHY, JYL, ICP, CMK), pp. 939–944.
DAC-1998-KimCLLPK #functional #modelling
Virtual Chip: Making Functional Models Work on Real Target Systems (NK, HC, SL, SL, ICP, CMK), pp. 170–173.
DAC-1998-YangKNCSRKLLKYKLHKKPPLHPK #development #named
MetaCore: An Application Specific DSP Development System (JHY, BWK, SJN, JHC, SWS, CHR, YSK, DHL, JYL, JSK, HDY, JYK, KML, CSH, IHK, JSK, KIP, KHP, YHL, SHH, ICP, CMK), pp. 800–803.
DATE-1998-YiCPHK #behaviour #multi #synthesis
Multiple Behavior Module Synthesis Based on Selective Groupings (JHY, HC, ICP, SHH, CMK), pp. 384–388.
DAC-1997-YimHPCYOPK #design #verification
A C-Based RTL Design Verification Methodology for Complex Microprocessor (JSY, YHH, CJP, HC, WSY, HSO, ICP, CMK), pp. 83–88.
DAC-1991-ParkK #automation #performance #scheduling
Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis (ICP, CMK), pp. 680–685.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.