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Travelled to:
3 × France
4 × Germany
Collaborated with:
A.Hekstra A.Radulescu E.Rijpkema J.Huisken K.G.W.Goossens P.Wielage V.Berg J.L.v.Meerbergen M.Cocco M.J.M.Heijligers K.Goossens O.P.Gangwal S.G.Pestana E.Waterlander M.Bekooij F.Harmsze S.Sawitzki A.v.d.Werf
Talks about:
network (4) guarante (3) design (3) decod (3) ldpc (3) chip (3) servic (2) effici (2) architectur (1) processor (1)

Person: John Dielissen

DBLP DBLP: Dielissen:John

Contributed to:

DATE 20072007
DATE Designers’ Forum 20062006
DATE 20052005
DATE DF 20042004
DATE v2 20042004
DATE 20032003
DATE 20012001

Wrote 7 papers:

DATE-2007-DielissenH #implementation #parallel
Non-fractional parallelism in LDPC decoder implementations (JD, AH), pp. 337–342.
DATE-DF-2006-DielissenHB #low cost
Low cost LDPC decoder for DVB-S2 (JD, AH, VB), pp. 130–135.
DATE-2005-GoossensDGPRR #design #network #performance #verification
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification (KG, JD, OPG, SGP, AR, ER), pp. 1182–1187.
DATE-DF-2004-CoccoDHHH #architecture #scalability
A Scalable Architecture for LDPC Decodin (MC, JD, MJMH, AH, JH), pp. 88–95.
DATE-v2-2004-RadulescuDGRW #abstraction #flexibility #interface #network #performance
An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration (AR, JD, KGWG, ER, PW), pp. 878–883.
DATE-2003-RijpkemaGRDMWW #design #network
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip (ER, KGWG, AR, JD, JLvM, PW, EW), pp. 10350–10355.
DATE-2001-DielissenMBHSHW #power management
Power-efficient layered turbo decoder processor (JD, JLvM, MB, FH, SS, JH, AvdW), pp. 246–251.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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