BibSLEIGH corpus
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Travelled to:
1 × France
2 × Germany
2 × USA
Collaborated with:
S.Neuendorffer J.Noguera Z.Guo B.Buyukkurt W.A.Najjar H.Yagi W.Rosenstiel J.Engblom J.Andrews M.Serughetti E.A.d.Kock W.J.M.Smits P.v.d.Wolf J.Brunel W.M.Kruijtzer P.Lieverse G.Essink
Talks about:
process (2) system (2) applic (2) fpgas (2) architectur (1) reconfigur (1) processor (1) synthesi (1) parallel (1) interfac (1)

Person: Kees A. Vissers

DBLP DBLP: Vissers:Kees_A=

Contributed to:

DATE 20112011
DAC 20092009
DATE 20052005
DATE 20032003
DAC 20002000

Wrote 5 papers:

DATE-2011-VissersNN #interface #realtime #synthesis #tool support #using
Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools (KAV, SN, JN), pp. 848–850.
DAC-2009-YagiREAVS #design
The wild west: conquest of complex hardware-dependent software design (HY, WR, JE, JA, KAV, MS), pp. 878–879.
DATE-2005-GuoBNV #c #generative
Optimized Generation of Data-Path from C Codes for FPGAs (ZG, BB, WAN, KAV), pp. 112–117.
DATE-2003-Vissers #architecture #configuration management #parallel
Parallel Processing Architectures for Reconfigurable Systems (KAV), pp. 10396–10397.
DAC-2000-KockSWBKLVE #modelling #named
YAPI: application modeling for signal processing systems (EAdK, WJMS, PvdW, JYB, WMK, PL, KAV, GE), pp. 402–405.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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