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Travelled to:
1 × France
1 × USA
2 × Germany
Collaborated with:
S.K.Lim A.Buyuktosunoglu P.Bose M.Vittes M.Ekpanyapong C.S.Ballapuram H.S.Lee G.H.Loh P.G.Emma K.Kailas V.Puente R.Yu A.Hartstein J.H.Moreno J.A.Darringer M.S.Gupta H.M.Jacobson I.Nair J.A.Rivers J.Shin A.Vega A.J.Weger
Talks about:
perform (2) power (2) microarchitectur (1) processor (1) floorplan (1) tradeoff (1) deliveri (1) challeng (1) topolog (1) thermal (1)

Person: Michael B. Healy

DBLP DBLP: Healy:Michael_B=

Contributed to:

HPCA 20142014
DATE 20122012
DATE 20112011
DATE 20062006

Wrote 4 papers:

HPCA-2014-EmmaBHKPYHBM #3d
3D stacking of high-performance processors (PGE, AB, MBH, KK, VP, RY, AH, PB, JHM), pp. 500–511.
DATE-2012-BoseBDGHJNRSVW #challenge #manycore #power management
Power management of multi-core chips: Challenges and pitfalls (PB, AB, JAD, MSG, MBH, HMJ, IN, JAR, JS, AV, AJW), pp. 977–982.
DATE-2011-HealyL #3d #network #novel
A novel TSV topology for many-tier 3D power-delivery networks (MBH, SKL), pp. 261–264.
DATE-2006-HealyVEBLLL #architecture #performance #trade-off
Microarchitectural floorplanning under performance and thermal tradeoff (MBH, MV, ME, CSB, SKL, HHSL, GHL), pp. 1288–1293.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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