BibSLEIGH corpus
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Travelled to:
1 × Germany
6 × USA
Collaborated with:
S.Mehrotra T.Thorolfsson M.B.Steer W.R.Davis K.Gonsalves W.Liu M.Basel S.Simovich T.Mills R.Puri D.Varma D.Edwards A.J.Weger A.Yang S.V.Kosonocky A.Fujimara R.Preston R.C.Sarma M.Walker S.Lipa E.C.Oh S.Melamed S.Luniya T.Doxsee S.Berkeley B.Shani K.Obermiller
Talks about:
design (3) generat (2) circuit (2) speed (2) wire (2) rule (2) high (2) hot (2) cad (2) interconnect (1)

Person: Paul D. Franzon

DBLP DBLP: Franzon:Paul_D=

Contributed to:

DATE 20102010
DAC 20092009
DAC 20082008
DAC 19991999
DAC 19951995
DAC 19941994
DAC 19921992

Wrote 8 papers:

DATE-2010-FranzonDT #3d #architecture #design
Creating 3D specific systems: Architecture, design and CAD (PDF, WRD, TT), pp. 1684–1688.
DAC-2009-ThorolfssonGF #3d #automation #case study #design
Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study (TT, KG, PDF), pp. 51–56.
DAC-2008-FranzonDSLOTMLDBSO #3d #design
Design and CAD for 3D integrated circuits (PDF, WRD, MBS, SL, ECO, TT, SM, SL, TD, SB, BS, KO), pp. 668–673.
DAC-2008-PuriVEWFYK #problem #question
Keeping hot chips cool: are IC thermal problems hot air? (RP, DV, DE, AJW, PDF, AY, SVK), pp. 634–635.
DAC-1999-FranzonBFMPSW #how #question
Parasitic Extraction Accuracy — How Much is Enough? (PDF, MB, AF, SM, RP, RCS, MW), p. 429.
DAC-1995-MehrotraFS #generative #performance
Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs (SM, PDF, MBS), pp. 381–387.
DAC-1994-MehrotraFL #approach #optimisation #probability
Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits (SM, PDF, WL), pp. 36–40.
DAC-1992-FranzonSSBMM #generative #tool support
Tools to Aid in Wiring Rule Generation for High Speed Interconnects (PDF, SS, MBS, MB, SM, TM), pp. 466–471.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.