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Travelled to:
1 × Germany
3 × USA
6 × France
Collaborated with:
S.L.Beux F.Gaffiot G.Nicolescu H.Li D.Navarro A.Fourmigue X.Letartre F.Tissafi-Drissi J.Trajkovic M.Briere F.Mieyeville Y.Thonnart J.Liu Z.Li C.Monat G.Beltrame E.M.Aboulhamid C.Piguet J.Gautier C.Heer U.Schlichtmann F.Teysseyre F.Cascio F.Cenni O.Guillaume P.Gaillardon M.H.B.Jamaa P.Morel J.Noël F.Clermidy G.Bois P.G.Paulin B.Courtois K.Chakrabarty N.Delorme M.Hampton J.Hartung L.Carrel T.Michalke R.Cao J.Billoudet J.Ferguson L.Couder J.Cayo A.Arriordaz K.Cheshmi X.Liu B.Girodias Y.Bouchebaba
Talks about:
optic (8) chip (6) system (5) design (5) architectur (3) network (3) interconnect (2) platform (2) thermal (2) integr (2)

Person: Ian O'Connor

DBLP DBLP: O'Connor:Ian

Contributed to:

DAC 20152015
DATE 20152015
DATE 20142014
DATE 20132013
DAC 20112011
DATE 20112011
DAC 20072007
DATE 20072007
DATE DF 20042004
DATE v1 20042004

Wrote 15 papers:

DAC-2015-LiBTO #communication #energy #performance
Complementary communication path for energy efficient on-chip optical interconnects (HL, SLB, YT, IO), p. 6.
DATE-2015-CaoBFCCAO #feature model #validation
LVS check for photonic integrated circuits: curvilinear feature extraction and validation (RC, JB, JF, LC, JC, AA, IO), pp. 1253–1256.
DATE-2015-LiFBLON #design
Thermal aware design method for VCSEL-based on-chip optical interconnect (HL, AF, SLB, XL, IO, GN), pp. 1120–1125.
DATE-2015-TeysseyreNOCCG #performance #set #simulation #using
Fast optical simulation from a reduced set of impulse responses using SystemC-AMS (FT, DN, IO, FC, FC, OG), pp. 405–409.
DATE-2014-BeuxLOCLTN #named #performance
Chameleon: Channel efficient Optical Network-on-Chip (SLB, HL, IO, KC, XL, JT, GN), pp. 1–6.
Optical look up table (ZL, SLB, CM, XL, IO), pp. 873–876.
DAC-2011-GaillardonBMNCO #3d #architecture #question #towards
Can we go towards true 3-D architectures? (PEG, MHBJ, PHM, JPN, FC, IO), pp. 282–283.
DATE-2011-BeuxTONBP #architecture #design
Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology (SLB, JT, IO, GN, GB, PGP), pp. 788–793.
DATE-2011-FourmigueBNAO #3d #architecture #evaluation #multi
Multi-granularity thermal evaluation of 3D MPSoC architectures (AF, GB, GN, EMA, IO), pp. 575–578.
DAC-2007-LiuONG #configuration management #design #logic #novel
Novel CNTFET-based Reconfigurable Logic Gate Design (JL, IO, DN, FG), pp. 276–277.
DATE-2007-BriereGBNMGO #assessment #framework #platform
System level assessment of an optical NoC in an MPSoC platform (MB, BG, YB, GN, FM, FG, IO), pp. 1084–1089.
Heterogeneous systems on chip and systems in package (IO, BC, KC, ND, MH, JH), pp. 737–742.
DATE-DF-2004-Tissafi-DrissiOG #automation #design #framework #multi #named #performance
RUNE: Platform for Automated Design of Integrated Multi-Domain Systems. Application to High-Speed CMOS Photoreceiver Front-Ends (FTD, IO, FG), pp. 16–21.
DATE-v1-2004-BriereCMMOG #behaviour #design #modelling #tool support
Design and Behavioral Modeling Tools for Optical Network-on-Chip (MB, LC, TM, FM, IO, FG), pp. 738–739.
DATE-v1-2004-PiguetGHOS #logic #power management
Extremely Low-Power Logic (CP, JG, CH, IO, US), pp. 656–663.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.