BibSLEIGH corpus
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Travelled to:
1 × China
1 × Switzerland
4 × France
4 × Germany
4 × USA
Collaborated with:
Y.Han Y.Hu H.Li L.Zhang G.Yan J.Ye Y.Wang S.Pan T.Lv J.Gao X.Hu K.Huang Q.Xu B.Fu J.Dong S.Ren S.Pei T.Zhang X.He B.Li S.Shan X.Li X.Zhang J.Li C.Wang J.Wang T.Wang H.Lu J.Wang L.Wang Y.Leiferman K.A.Kwiat B.Liu H.Liu J.Gong Y.Li M.Guo X.Liang Y.Yu Y.Liu S.Hu J.Wu Y.Shi Y.Jin J.Deng Y.Fang Z.Du O.Temam P.Ienne D.Novo Y.Chen C.Wu
Talks about:
base (7) power (5) chip (5) processor (4) scheme (4) memori (4) toler (4) fault (4) test (4) awar (4)

Person: Xiaowei Li

DBLP DBLP: Li:Xiaowei

Contributed to:

DAC 20152015
DATE 20152015
DATE 20142014
DAC 20132013
DATE 20132013
DATE 20122012
HPCA 20122012
DAC 20112011
DATE 20112011
DATE 20102010
SAC 20102010
DATE 20092009
DATE 20082008
HCI p4 20072007

Wrote 31 papers:

DAC-2015-LiuHWSJHL #assessment #detection #smarttech
Impact assessment of net metering on smart home cyberattack detection (YL, SH, JW, YS, YJ, YH, XL), p. 6.
DAC-2015-WangH0LL #logic #memory management #named
ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing (YW, YH, LZ, HL, XL), p. 6.
DAC-2015-WangHWLL #assembly #memory management #named
RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory (YW, YH, CW, HL, XL), p. 6.
DATE-2015-DengFDWLTINLCW #fault #hardware #network
Retraining-based timing error mitigation for hardware neural networks (JD, YF, ZD, YW, HL, OT, PI, DN, XL, YC, CW), pp. 593–596.
DATE-2014-HeYH0 #design #named #power management
SuperRange: Wide operational range power delivery design for both STV and NTV computing (XH, GY, YH, XL), pp. 1–6.
DATE-2014-LiSH0 #in memory #memory management #named
Partial-SET: Write speedup of PCM main memory (BL, SS, YH, XL), pp. 1–4.
DATE-2014-WangLLW0 #design #functional #generative #testing
Functional test generation guided by steady-state probabilities of abstract design (JW, HL, TL, TW, XL), pp. 1–4.
DAC-2013-LuYHF0 #named
RISO: relaxed network-on-chip isolation for cloud processors (HL, GY, YH, BF, XL), p. 6.
DATE-2013-HuYH0 #concurrent #low cost #multi #named #thread
Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications (XH, GY, YH, XL), pp. 208–213.
DATE-2013-LiYHL #adaptation #named #smarttech #user interface
SmartCap: user experience-oriented power adaptation for smartphone’s application processor (XL, GY, YH, XL), pp. 57–60.
DATE-2013-ZhangYH0 #testing
Capturing post-silicon variation by layout-aware path-delay testing (XZ, JY, YH, XL), pp. 288–291.
DATE-2012-GaoWHZL #clustering #concurrent #debugging #manycore
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems (JG, JW, YH, LZ, XL), pp. 27–32.
DATE-2012-HuangHLLLG #power management
Off-path leakage power aware routing for SRAM-based FPGAs (KH, YH, XL, BL, HL, JG), pp. 87–92.
HPCA-2012-YanLHLGL #architecture #hybrid #manycore #named #performance
AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture (GY, YL, YH, XL, MG, XL), pp. 287–298.
Wear rate leveling: lifetime enhancement of PRAM with endurance variation (JD, LZ, YH, YW, XL), pp. 972–977.
DATE-2011-GaoHL #debugging #multi
Eliminating data invalidation in debugging multiple-clock chips (JG, YH, XL), pp. 691–696.
DATE-2011-HuangHL #fault
Cross-layer optimized placement and routing for FPGA soft error mitigation (KH, YH, XL), pp. 58–63.
DATE-2011-PanHHL #effectiveness
A cost-effective substantial-impact-filter based method to tolerate voltage emergencies (SP, YH, XH, XL), pp. 311–315.
DATE-2011-WangZHLL #memory management
Flex memory: Exploiting and managing abundant off-chip optical bandwidth (YW, LZ, YH, HL, XL), pp. 968–973.
DATE-2011-YeHL #fault #multi #on the #using
On diagnosis of multiple faults using compacted responses (JY, YH, XL), pp. 679–684.
Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs (BF, YH, HL, XL), pp. 933–936.
DATE-2010-PanHL #fault #named
IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults (SP, YH, XL), pp. 238–243.
DATE-2010-PeiLL #generative #testing
An on-chip clock generation scheme for faster-than-at-speed delay testing (SP, HL, XL), pp. 1353–1356.
DATE-2010-YeHL #fault #multi
Diagnosis of multiple arbitrary faults with mask and reinforcement effect (JY, YH, XL), pp. 885–890.
DATE-2010-ZhangLL #approach #markov #modelling #simulation #using #verification
An abstraction-guided simulation approach using Markov models for microprocessor verification (TZ, TL, XL), pp. 484–489.
DATE-2010-ZhangYDHRL #manycore #symmetry
Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors (LZ, YY, JD, YH, SR, XL), pp. 1566–1571.
SAC-2010-WangLRKL #distributed #information management
Improving complex distributed software system availability through information hiding (LW, YL, SR, KAK, XL), pp. 452–456.
DATE-2009-YanHL #detection #fault #online
A unified online Fault Detection scheme via checking of Stability Violation (GY, YH, XL), pp. 496–501.
DATE-2008-LiXHL #named #reduction #testing
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing (JL, QX, YH, XL), pp. 1184–1189.
DATE-2008-ZhangHXL #fault #manycore #using
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology (LZ, YH, QX, XL), pp. 891–896.
HCI-AS-2007-ZhangLL #algorithm #fault #random
A Routing Algorithm for Random Error Tolerance in Network-on-Chip (LZ, HL, XL), pp. 1210–1219.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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