Travelled to:1 × China
2 × France
3 × Germany
Collaborated with:S.Hong Y.Lee ∅ N.Vijaykrishnan M.T.Kandemir M.J.Irwin T.Mahmood J.Kim J.Lee J.S.Hu H.Saputra R.R.Brooks W.Zhang
Talks about:cach (4) architectur (2) power (2) dram (2) tag (2) threshold (1) skinflint (1) instruct (1) insensit (1) behavior (1)
Person: Soontae Kim
DBLP: Kim:Soontae
Contributed to:
2013
20132010200620042003Wrote 7 papers:
- DATE-2013-HongK #architecture #named
- AVICA: an access-time variation insensitive L1 cache architecture (SH, SK), pp. 65–70.
- HPCA-2013-LeeKH0 #power management
- Skinflint DRAM system: Minimizing DRAM chip writes for low power (YL, SK, SH, JL), pp. 25–34.
- HPCA-2013-MahmoodKH #adaptation #architecture #named #scalability
- Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling (TM, SK, SH), pp. 532–541.
- DATE-2010-KimKL #named #reliability #similarity
- SimTag: Exploiting tag bits similarity to improve the reliability of the data caches (JK, SK, YL), pp. 941–944.
- DATE-2006-Kim #fault
- Area-efficient error protection for caches (SK), pp. 1282–1287.
- DATE-v1-2004-HuVKKI #reduction #reuse #scheduling
- Scheduling Reusable Instructions for Power Reduction (JSH, NV, SK, MTK, MJI), pp. 148–155.
- DATE-2003-SaputraVKIBKZ #behaviour #encryption #energy
- Masking the Energy Behavior of DES Encryption (HS, NV, MTK, MJI, RRB, SK, WZ), pp. 10084–10089.