BibSLEIGH — Vivek

Travelled to:

1 × France
10 × USA
2 × Germany

Collaborated with:

J.Tschanz S.Borkar T.Karnik K.A.Bowman Y.Ye K.Roy L.Wei ∅ Z.Chen G.Sery P.Pant A.Chatterjee M.M.Khellah S.M.Burns A.Keshavarzi S.Narendra N.Azizi F.N.Najm S.Lu W.Zhang M.T.Kandemir N.Vijaykrishnan M.J.Irwin D.Somasekhar S.H.Choi M.Johnson M.Ketkar N.Menezes C.Wilkerson S.Y.Borkar V.Govindarajulu A.Vassighi G.Schrom S.Lee G.Chrysler M.Sachdev M.Nicolaidis L.Anghel N.Zergainoh Y.Zorian C.Tokunaga A.Raychowdhury J.Kulkarni D.Avresky

Talks about:

circuit (8) design (8) cmos (6) variat (4) power (4) optim (4) low (4) techniqu (3) voltag (3) microprocessor (2)

Person: Vivek De

DBLP: De:Vivek

Contributed to:

2013

2012

2009

2007

2005

2004

2003

2002

2000

1999

1998

1997

Wrote 16 papers:

DATE-2013-De #design: Near-threshold voltage design in nanoscale CMOS (VD), p. 612.
DATE-2012-NicolaidisAZZKBTLTRKKDA #design #reliability: Design for test and reliability in ultimate CMOS (MN, LA, NEZ, YZ, TK, KAB, JT, SLL, CT, AR, MMK, JK, VD, DA), pp. 677–682.
DAC-2009-BowmanTWLKDB: Circuit techniques for dynamic variation tolerance (KAB, JT, CW, SLL, TK, VD, SYB), pp. 4–7.
DAC-2007-BurnsKMBTD #analysis #comparative #design #statistics: Comparative Analysis of Conventional and Statistical Design Techniques (SMB, MK, NM, KAB, JT, VD), pp. 238–243.
DAC-2005-AziziKDN #design #power management #scalability: Variations-aware low-power design with voltage scaling (NA, MMK, VD, FNN), pp. 529–534.
DAC-2005-TschanzBD: Variation-tolerant circuits: circuit solutions and techniques (JT, KAB, VD), pp. 762–763.
DAC-2004-BorkarKD #challenge #design #reliability: Design and reliability challenges in nanometer technologies (SB, TK, VD), p. 75.
DAC-2004-VassighiKNSYLCSD #design #optimisation: Design optimizations for microprocessors at low temperature (AV, AK, SN, GS, YY, SL, GC, MS, VD), pp. 2–5.
DAC-2003-BorkarKNTKD #architecture #parametricity: Parameter variations and impact on circuits and microarchitecture (SB, TK, SN, JT, AK, VD), pp. 338–342.
DATE-2003-ZhangKVID #compilation #energy: Compiler Support for Reducing Leakage Energy Consumption (WZ, MTK, NV, MJI, VD), pp. 11146–11147.
DAC-2002-KarnikYTWBGDB #optimisation #performance: Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors (TK, YY, JT, LW, SMB, VG, VD, SB), pp. 486–491.
DAC-2002-SeryBD #question #why: Life is CMOS: why chase the life after? (GS, SB, VD), pp. 78–83.
DAC-2000-SomasekharCRYD #analysis: Dynamic noise analysis in precharge-evaluate circuits (DS, SHC, KR, YY, VD), p. 243.
DAC-1999-WeiCRYD #design #power management: Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications (LW, ZC, KR, YY, VD), pp. 430–435.
DAC-1998-WeiCJRD #design #optimisation #performance: Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits (LW, ZC, MJ, KR, VD), pp. 489–494.
DAC-1997-PantDC #energy #logic #network #optimisation #power management #random: Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks (PP, VD, AC), pp. 403–408.