Travelled to:1 × Germany
5 × USA
Collaborated with:V.De K.A.Bowman T.Karnik S.M.Burns S.Borkar S.Lu M.Ketkar N.Menezes S.Narendra A.Keshavarzi C.Wilkerson S.Y.Borkar Y.Ye L.Wei V.Govindarajulu M.Nicolaidis L.Anghel N.Zergainoh Y.Zorian C.Tokunaga A.Raychowdhury M.M.Khellah J.Kulkarni D.Avresky
Talks about:circuit (4) techniqu (3) variat (3) design (2) toler (2) microarchitectur (1) microprocessor (1) simultan (1) statist (1) reliabl (1)
Person: James Tschanz
DBLP: Tschanz:James
Contributed to:
2012
20092007200520032002Wrote 6 papers:
- DATE-2012-NicolaidisAZZKBTLTRKKDA #design #reliability
- Design for test and reliability in ultimate CMOS (MN, LA, NEZ, YZ, TK, KAB, JT, SLL, CT, AR, MMK, JK, VD, DA), pp. 677–682.
- DAC-2009-BowmanTWLKDB
- Circuit techniques for dynamic variation tolerance (KAB, JT, CW, SLL, TK, VD, SYB), pp. 4–7.
- DAC-2007-BurnsKMBTD #analysis #comparative #design #statistics
- Comparative Analysis of Conventional and Statistical Design Techniques (SMB, MK, NM, KAB, JT, VD), pp. 238–243.
- DAC-2005-TschanzBD
- Variation-tolerant circuits: circuit solutions and techniques (JT, KAB, VD), pp. 762–763.
- DAC-2003-BorkarKNTKD #architecture #parametricity
- Parameter variations and impact on circuits and microarchitecture (SB, TK, SN, JT, AK, VD), pp. 338–342.
- DAC-2002-KarnikYTWBGDB #optimisation #performance
- Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors (TK, YY, JT, LW, SMB, VG, VD, SB), pp. 486–491.