BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × Germany
5 × USA
Collaborated with:
V.De K.A.Bowman T.Karnik S.M.Burns S.Borkar S.Lu M.Ketkar N.Menezes S.Narendra A.Keshavarzi C.Wilkerson S.Y.Borkar Y.Ye L.Wei V.Govindarajulu M.Nicolaidis L.Anghel N.Zergainoh Y.Zorian C.Tokunaga A.Raychowdhury M.M.Khellah J.Kulkarni D.Avresky
Talks about:
circuit (4) techniqu (3) variat (3) design (2) toler (2) microarchitectur (1) microprocessor (1) simultan (1) statist (1) reliabl (1)

Person: James Tschanz

DBLP DBLP: Tschanz:James

Contributed to:

DATE 20122012
DAC 20092009
DAC 20072007
DAC 20052005
DAC 20032003
DAC 20022002

Wrote 6 papers:

DATE-2012-NicolaidisAZZKBTLTRKKDA #design #reliability
Design for test and reliability in ultimate CMOS (MN, LA, NEZ, YZ, TK, KAB, JT, SLL, CT, AR, MMK, JK, VD, DA), pp. 677–682.
Circuit techniques for dynamic variation tolerance (KAB, JT, CW, SLL, TK, VD, SYB), pp. 4–7.
DAC-2007-BurnsKMBTD #analysis #comparative #design #statistics
Comparative Analysis of Conventional and Statistical Design Techniques (SMB, MK, NM, KAB, JT, VD), pp. 238–243.
Variation-tolerant circuits: circuit solutions and techniques (JT, KAB, VD), pp. 762–763.
DAC-2003-BorkarKNTKD #architecture #parametricity
Parameter variations and impact on circuits and microarchitecture (SB, TK, SN, JT, AK, VD), pp. 338–342.
DAC-2002-KarnikYTWBGDB #optimisation #performance
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors (TK, YY, JT, LW, SMB, VG, VD, SB), pp. 486–491.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.