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Travelled to:
3 × Germany
3 × USA
4 × France
Collaborated with:
N.Fournel S.Lagraa A.Termier A.Bouchhima P.G.d.Massas P.Gomez A.Faravelon S.Foroutan A.Sheibanyrad L.Michel A.E.Mrabti P.Gerin X.Guerin A.A.Jerraya J.Brunel W.M.Kruijtzer H.J.H.N.Kenter L.Pasquier E.A.d.Kock W.J.M.Smits
Talks about:
simul (5) memori (3) mpsoc (3) processor (2) implement (2) interfac (2) effici (2) trace (2) mine (2) data (2)

Person: Frédéric Pétrot

DBLP DBLP: P=eacute=trot:Fr=eacute=d=eacute=ric

Contributed to:

DATE 20152015
DATE 20142014
DATE 20132013
DAC 20122012
DATE 20112011
DATE 20092009
DATE 20082008
DAC 20062006
DATE 20032003
DAC 20002000

Wrote 11 papers:

DATE-2015-FaravelonFP #branch #performance #predict #simulation
Fast and accurate branch predictor simulation (AF, NF, FP), pp. 317–320.
DATE-2014-LagraaTP #data mining #mining #scalability #simulation #using
Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces (SL, AT, FP), pp. 1–6.
DATE-2013-LagraaTP #concurrent #data access #data mining #identification #memory management #mining #simulation
Data mining MPSoC simulation traces to identify concurrent memory access patterns (SL, AT, FP), pp. 755–760.
DAC-2012-ForoutanSP #3d #interface #low cost #using
Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces (SF, AS, FP), pp. 366–375.
DATE-2011-MichelFP #embedded #simulation
Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation (LM, NF, FP), pp. 277–280.
DATE-2009-MrabtiPB #approach #design
Extending IP-XACT to support an MDE based approach for SoC design (AEM, FP, AB), pp. 586–589.
DATE-2008-GerinGP #implementation #performance #simulation
Efficient Implementation of Native Software Simulation for MPSoC (PG, XG, FP), pp. 676–681.
DATE-2008-MassasP #comparison #manycore #memory management #policy
Comparison of memory write policies for NoC based Multicore Cache Coherent Systems (PGdM, FP), pp. 997–1002.
DAC-2006-JerrayaBP #abstraction #interface #modelling #multi #programming
Programming models and HW-SW interfaces abstraction for multi-processor SoC (AAJ, AB, FP), pp. 280–285.
DATE-2003-PetrotG #api #implementation #lightweight #multi #thread
Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect (FP, PG), pp. 20051–20056.
DAC-2000-BrunelKKPPKS #communication
COSY communication IP’s (JYB, WMK, HJHNK, FP, LP, EAdK, WJMS), pp. 406–409.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.