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Travelled to:
1 × India
2 × France
2 × Germany
2 × Spain
5 × USA
Collaborated with:
F.J.Cazorla E.Quiñones C.Hernández L.Kosmidis A.González T.Vardanega B.Maric M.Valero J.Carretero X.Vera J.Jalle G.Fernandez P.Chaparro S.Milutinovic E.Mezzetti T.M.Jones M.F.P.O'Boyle F.Wartel J.Espinosa D.d.Andrés J.C.Ruiz M.Slijepcevic G.Farrall C.Curtsinger E.D.Berger T.Ramírez M.Monchiero L.Fossati M.Zulianello S.Girbal M.Moretó A.Grasset S.Yehia Enrique Díaz Mikel Fernández Irune Agirre Mikel Azkarate-askasua A.Gogonel A.Baldovin Z.R.Stephenson B.Triquet C.Lo I.Broster L.Cucu-Grosjean
Talks about:
time (12) cach (8) multicor (5) system (5) probabilist (4) softwar (4) analysi (4) low (4) reliabl (3) perform (3)

Person: Jaume Abella

DBLP DBLP: Abella:Jaume

Contributed to:

DAC 20152015
DATE 20152015
SAC 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DATE 20132013
HPCA 20112011
DATE 20102010
HPCA 20102010
HPCA 20052005
HPCA 20042004
Ada-Europe 20172017

Wrote 23 papers:

DAC-2015-EspinosaHAAR #analysis #correlation #robust #set #verification
Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification (JE, CH, JA, DdA, JCR), p. 6.
DAC-2015-FernandezJAQVC #bound #realtime
Increasing confidence on measurement-based contention bounds for real-time round-robin buses (GF, JJ, JA, EQ, TV, FJC), p. 6.
DAC-2015-FernandezJAQVC15a #manycore #off the shelf #resource management
Resource usage templates and signatures for COTS multicore processors (GF, JJ, JA, EQ, TV, FJC), p. 6.
DAC-2015-MilutinovicQAC #estimation #named #performance
PACO: fast average-performance estimation for time-randomized caches (SM, EQ, JA, FJC), p. 6.
DATE-2015-HernandezA #low cost #safety
Low-cost checkpointing in automotive safety-relevant systems (CH, JA), pp. 91–96.
DATE-2015-WartelKGBSTQLMB #analysis #case study #hardware #platform
Timing analysis of an avionics case study on complex hardware/software platforms (FW, LK, AG, AB, ZRS, BT, EQ, CL, EM, IB, JA, LCG, TV, FJC), pp. 397–402.
SAC-2015-FernandezAQVFZC #multi #off the shelf
Introduction to partial time composability for COTS multicores (GF, JA, EQ, TV, LF, MZ, FJC), pp. 1955–1956.
DAC-2014-HernandezA #detection #fault #named #safety
LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems (CH, JA), p. 6.
DAC-2014-KosmidisQAFWC #certification #hardware
Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware (LK, EQ, JA, GF, FW, FJC), p. 6.
DAC-2014-SlijepcevicKAQC #manycore #realtime
Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems (MS, LK, JA, EQ, FJC), p. 6.
DATE-2014-JalleKAQC #design #manycore
Bus designs for time-probabilistic multicore processors (JJ, LK, JA, EQ, FJC), pp. 1–6.
DAC-2013-GirbalMGAQCY #convergence #on the
On the convergence of mainstream and mission-critical markets (SG, MM, AG, JA, EQ, FJC, SY), p. 10.
DAC-2013-MaricAV #adaptation #energy #hybrid #named #predict #reliability
APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation (BM, JA, MV), p. 8.
DATE-2013-KosmidisAQC #design #realtime
A cache design for probabilistically analysable real-time systems (LK, JA, EQ, FJC), pp. 513–518.
DATE-2013-KosmidisCQABC #analysis #design #probability
Probabilistic timing analysis on conventional cache designs (LK, CC, EQ, JA, EDB, FJC), pp. 603–606.
DATE-2013-MaricAV #architecture #hybrid #performance #reliability #using
Efficient cache architectures for reliable hybrid voltage operation using EDC codes (BM, JA, MV), pp. 917–920.
HPCA-2011-CarreteroVARMG #hardware #process #using
Hardware/software-based diagnosis of load-store queues using expandable activity logs (JC, XV, JA, TR, MM, AG), pp. 321–331.
The split register file (JA, JC, PC, XV), pp. 945–948.
High-Performance low-vcc in-order core (JA, PC, XV, JC, AG), pp. 1–11.
HPCA-2005-JonesOAG #queue #reduction
Software Directed Issue Queue Power Reduction (TMJ, MFPO, JA, AG), pp. 144–153.
HPCA-2004-AbellaG #distributed #queue
Low-Complexity Distributed Issue Queue (JA, AG), pp. 73–83.
AdaEurope-2017-DiazFKMHAC #analysis #bound #manycore #named #probability
MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding (ED, MF, LK, EM, CH, JA, FJC), pp. 102–118.
AdaEurope-2017-MilutinovicAAAM #reliability
Software Time Reliability in the Presence of Cache Memories (SM, JA, IA, MAa, EM, TV, FJC), pp. 233–249.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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