BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
2 × Germany
5 × France
6 × USA
Collaborated with:
G.G.E.Gielen W.Daems P.Vanassche T.Eeckelaert M.Steyaert S.Donnay R.Schoofs J.Vandenbussche W.Kruiskamp D.Leenaerts K.Lampaert G.V.d.Plas L.R.Carley R.A.Rutenbar F.Leyn A.v.d.Bosch W.v.Bokhoven K.Swings C.D.Ranter B.D.Muer P.J.Vancorenland
Talks about:
analog (8) model (6) circuit (5) design (5) perform (4) signal (4) methodolog (3) synthesi (3) hierarch (3) system (3)

Person: Willy M. C. Sansen

DBLP DBLP: Sansen:Willy_M=_C=

Contributed to:

DATE 20072007
DAC 20062006
DATE 20032003
DAC 20022002
DATE 20022002
DATE 20012001
DAC 20002000
DAC 19991999
DATE 19981998
ED&TC 19971997
DAC 19961996
DAC 19951995

Wrote 17 papers:

DATE-2007-EeckelaertSGSS #performance #synthesis
An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection (TE, RS, GGEG, MS, WMCS), pp. 81–86.
DAC-2006-EeckelaertSGSS #design #optimisation #standard
Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard (TE, RS, GGEG, MS, WMCS), pp. 25–30.
DATE-2003-EeckelaertDGS #modelling #performance
Generalized Posynomial Performance Modeling (TE, WD, GGEG, WMCS), pp. 10250–10255.
DATE-2003-VanasscheGS #analysis #detection #domain model #modelling
Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors (PV, GGEG, WMCS), pp. 10238–10243.
DAC-2002-DaemsGS #modelling #performance
An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits (WD, GGEG, WMCS), pp. 431–436.
DAC-2002-VanasscheGS #behaviour #modelling
Behavioral modeling of (coupled) harmonic oscillators (PV, GGEG, WMCS), pp. 536–541.
DATE-2002-DaemsGS #approach #linear #performance
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics (WD, GGEG, WMCS), pp. 268–273.
DATE-2002-VanasscheGS #behaviour #matrix #modelling #using
Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices (PV, GGEG, WMCS), pp. 279–284.
DATE-2001-VanasscheGS #exponential #performance #simulation #using
Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model (PV, GGEG, WMCS), pp. 169–175.
DAC-2000-PlasVDBGS #design
Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter (GVdP, JV, WD, AvdB, GGEG, WMCS), pp. 452–457.
DAC-2000-RanterMPVSGS #automation #design #layout #named
CYCLONE: automated design and layout of RF LC-oscillators (CDR, BDM, GVdP, PJV, MS, GGEG, WMCS), pp. 11–14.
DAC-1999-DaemsGS #analysis #complexity #reduction
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits (WD, GGEG, WMCS), pp. 958–963.
DATE-1998-VandenbusscheDLGS #design #interface #specification #top-down
Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon (JV, SD, FL, GGEG, WMCS), pp. 716–720.
EDTC-1997-DonnayGSKLB #interface #synthesis
High-level synthesis of analog sensor interface front-ends (SD, GGEG, WMCS, WK, DL, WvB), pp. 56–60.
DAC-1996-CarleyGRS #synthesis #tool support
Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies (LRC, GGEG, RAR, WMCS), pp. 298–303.
Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits (KL, GGEG, WMCS), pp. 445–449.
EDAC-1994-DonnaySGSKL #automation #design
A Methodology for Analog Design Automation in Mixed-Signal ASICs (SD, KS, GGEG, WMCS, WK, DL), pp. 530–534.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.