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Travelled to:
1 × France
20 × USA
4 × Germany
Collaborated with:
L.R.Carley A.Singhee E.C.Carlson S.K.Tiwary S.A.Kravitz Z.Xiu W.Zhang X.Li C.F.Fang B.Basaran S.Nag D.E.Setliff R.Phelps M.Krasnicki S.Singhal P.K.Tiwary G.Frehse B.H.Krogh G.Nam K.A.Sakallah E.S.Ochotta P.C.Maulik R.E.Bryant R.Harjani T.H.Y.Meng J.D.Ma J.D.Z.Ma S.M.Fowler M.Püschel T.Chen H.Liu G.G.E.Gielen W.M.C.Sansen T.N.Mudge R.M.Lougheed D.E.Atkins S.Saxena A.J.Strojwas P.Groeneveld J.W.Pitera J.Chen G.Zhang E.A.Dengi R.A.Rohrer J.R.Hellums A.Kuehlmann A.Bose D.E.Corman R.M.Manning A.Newman Y.Chien D.Chen J.Lou G.Ma T.Mukherjee A.R.Bonaccio E.Perea R.Pitts C.Sodini J.Wieser D.L.Harame K.Johnson P.Kempf R.Rofougaran J.Spoto
Talks about:
analog (10) circuit (9) synthesi (8) design (5) base (5) statist (4) perform (4) effici (4) applic (4) simul (4)

Person: Rob A. Rutenbar

DBLP DBLP: Rutenbar:Rob_A=

Contributed to:

DAC 20142014
DAC 20132013
DAC 20102010
DAC 20092009
DAC 20082008
DATE 20082008
DAC 20072007
DATE 20072007
DAC 20062006
DATE 20062006
DAC 20052005
DATE 20052005
DAC 20042004
DAC 20032003
DAC 20022002
DATE 20012001
DAC 20002000
DAC 19991999
DAC 19961996
DAC 19941994
DAC 19921992
DAC 19901990
DAC 19891989
DAC 19881988
DAC 19871987
DAC 19861986
DAC 19821982

Wrote 35 papers:

DAC-2014-Rutenbar #automation #design #education
The First EDA MOOC: Teaching Design Automation to Planet Earth (RAR), p. 6.
DAC-2013-ZhangLSSR #automation #clustering
Automatic clustering of wafer spatial signatures (WZ, XL, SS, AJS, RAR), p. 6.
Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference (WZ, XL, RAR), pp. 262–267.
Oil fields, hedge funds, and drugs (PG, RAR, JWP, ECC, JC), pp. 416–417.
DAC-2008-KuehlmannBCRMN #verification
Verifying really complex systems: on earth and beyond (AK, AB, DEC, RAR, RMM, AN), pp. 552–553.
DATE-2008-SingheeSR #correlation #kernel #performance #statistics
Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing (AS, SS, RAR), pp. 856–861.
DAC-2007-SingheeR #performance #statistics
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting (AS, RAR), pp. 256–261.
DATE-2007-SingheeR #monte carlo #novel #performance #simulation #statistics
Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application (AS, RAR), pp. 1379–1384.
DAC-2006-SingheeFMR #probability #statistics #tool support #towards
Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools (AS, CFF, JDM, RAR), pp. 167–172.
DAC-2006-TiwaryTR #design #generative
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration (SKT, PKT, RAR), pp. 31–36.
DATE-2006-FrehseKR #abstraction #refinement #using #verification
Verifying analog oscillator circuits using forward/backward abstraction refinement (GF, BHK, RAR), pp. 257–262.
DAC-2005-TiwaryR #megamodelling #on-demand #scalability
Scalable trajectory methods for on-demand analog macromodel extraction (SKT, RAR), pp. 403–408.
Timing-driven placement by grid-warping (ZX, RAR), pp. 585–591.
DATE-2005-ChienCLMRM #optimisation #pipes and filters
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters (YTC, DC, JHL, GKM, RAR, TM), pp. 279–280.
DAC-2004-RutenbarBMPPSW #question
Will Moore’s Law rule in the land of analog? (RAR, ARB, THYM, EP, RP, CS, JW), p. 633.
DAC-2004-XiuMFR #scalability
Large-scale placement by grid-warping (ZX, JDZM, SMF, RAR), pp. 351–356.
DAC-2004-ZhangDRRC #performance #synthesis #towards
A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits (GZ, EAD, RAR, RAR, LRC), pp. 155–158.
DAC-2003-FangRPC #modelling #performance #static analysis #towards
Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling (CFF, RAR, MP, TC), pp. 496–501.
Mixed signals on mixed-signal: the right next technology (RAR, DLH, KJ, PK, THYM, RR, JS), pp. 278–279.
DAC-2002-LiuSRC #data mining #design #megamodelling #mining #scalability
Remembrance of circuits past: macromodeling by data mining in large analog design spaces (HL, AS, RAR, LRC), pp. 437–442.
DATE-2001-NamSR #approach #incremental #satisfiability
A boolean satisfiability-based incremental rerouting approach with application to FPGAs (GJN, KAS, RAR), pp. 560–565.
DAC-2000-PhelpsKRCH #case study #synthesis
A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC (RP, MK, RAR, LRC, JRH), pp. 1–6.
DAC-1999-KrasnickiPRC #named #performance #synthesis
MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells (MK, RP, RAR, LRC), pp. 945–950.
DAC-1996-BasaranR #algorithm #constraints #performance
An O(n) Algorithm for Transistor Stacking with Performance Constraints (BB, RAR), pp. 221–226.
DAC-1996-CarleyGRS #synthesis #tool support
Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies (LRC, GGEG, RAR, WMCS), pp. 298–303.
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs (SN, RAR), pp. 301–307.
DAC-1994-OchottaRC #agile #named #synthesis #tool support
ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits (ESO, RAR, LRC), pp. 24–30.
DAC-1992-MaulikCR #approach #programming #synthesis
A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis (PCM, LRC, RAR), pp. 698–703.
DAC-1990-CarlsonR #algorithm #design #evaluation #parallel #performance #verification
Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW (ECC, RAR), pp. 253–259.
DAC-1989-KravitzBR #parallel #simulation
Massively Parallel Switch-Level Simulation: A Feasibility Study (SAK, REB, RAR), pp. 91–97.
DAC-1989-SetliffR #automation #named #physics #synthesis
ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software (DES, RAR), pp. 543–548.
DAC-1988-CarlsonR #verification
Mask Verification on the Connection Machine (ECC, RAR), pp. 134–140.
DAC-1987-HarjaniRC #framework #knowledge-based #prototype #synthesis
A Prototype Framework for Knowledge-Based Analog Circuit Synthesis (RH, RAR, LRC), pp. 42–49.
DAC-1986-KravitzR #multi
Multiprocessor-based placement by simulated annealing (SAK, RAR), pp. 567–573.
DAC-1982-MudgeRLA #image #layout #validation
Cellular image processing techniques for VLSI circuit layout validation and routing (TNM, RAR, RML, DEA), pp. 537–543.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.