Travelled to:1 × France
2 × Germany
5 × USA
Collaborated with:A.Chattopadhyay M.H.Neishaburi H.H.Y.Chan K.Radecka A.Kazamiphur J.Chenard C.Y.Chu M.Popovic A.Grbic S.D.Brown S.Caranci R.Grindley M.Gusat K.Loveless N.Manjikian S.Srbljic Z.G.Vranesic G.G.Lemieux M.Stumm
Talks about:design (3) multiprocessor (2) system (2) revers (2) debug (2) clock (2) reconfigur (1) methodolog (1) technolog (1) implement (1)
Person: Zeljko Zilic
DBLP: Zilic:Zeljko
Contributed to:
2010
2009200820072007200519981996Wrote 8 papers:
- DATE-2010-NeishaburiZ #clustering #debugging #performance
- Enabling efficient post-silicon debug by clustering of hardware-assertions (MHN, ZZ), pp. 985–988.
- DAC-2009-ChattopadhyayZ #configuration management
- Serial reconfigurable mismatch-tolerant clock distribution (AC, ZZ), pp. 611–612.
- DATE-2008-ChattopadhyayZ #debugging #online
- Built-in Clock Skew System for On-line Debug and Repair (AC, ZZ), pp. 248–251.
- DAC-2007-ChanZ #modelling
- Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops (HHYC, ZZ), pp. 430–435.
- DATE-2007-ZilicRK #specification
- Reversible circuit technology mapping from non-reversible specifications (ZZ, KR, AK), pp. 558–563.
- DAC-2005-ChenardCZP #design
- Design methodology for wireless nodes with printed antennas (JSC, CYC, ZZ, MP), pp. 291–296.
- DAC-1998-GrbicBCGGLLMSSVZ #design #implementation #multi
- Design and Implementation of the NUMAchine Multiprocessor (AG, SDB, SC, RG, MG, GGL, KL, NM, SS, MS, ZGV, ZZ), pp. 66–69.
- DAC-1996-BrownMVCGGGLZS #design #experience #multi #programmable #scalability #tool support #using
- Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools (SDB, NM, ZGV, SC, AG, RG, MG, KL, ZZ, SS), pp. 427–432.