BibSLEIGH — Sandeep_K

Travelled to:

4 × France
5 × Germany
7 × USA

Collaborated with:

M.A.Breuer I.Parulkar D.Shin C.Chen B.Cha Y.Gao M.Pedram M.S.Quasem S.Wang W.Fang H.Hsiung M.Mirza-Aghatabar L.Chen S.Lin R.Srinivasan Y.Wang S.Nazarian

Talks about:

test (8) delay (5) bist (5) schedul (4) toler (4) fault (4) resourc (3) generat (3) applic (3) error (3)

Person: Sandeep K. Gupta

DBLP: Gupta:Sandeep_K=

Contributed to:

2014

2013

2012

2011

2010

2006

2001

1998

1997

1996

1995

1994

1993

Wrote 20 papers:

DATE-2014-GaoGWP #energy #fault #fault tolerance #framework #in the cloud #scheduling: An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems (YG, SKG, YW, MP), pp. 1–6.
DATE-2013-ChaG #approach #detection #effectiveness #metric: Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost (BC, SKG), pp. 1265–1270.
DATE-2013-GaoGB #fault tolerance #scheduling #using: Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors (YG, SKG, MAB), pp. 927–932.
DATE-2012-HsuingCG: Salvaging chips with caches beyond repair (HH, BC, SKG), pp. 1263–1268.
DATE-2011-ShinG #fault: A new circuit simplification method for error tolerant applications (DS, SKG), pp. 1566–1571.
DATE-2010-Mirza-AghatabarBG #algorithm #pipes and filters: Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules (MMA, MAB, SKG), pp. 1249–1254.
DATE-2010-ShinG #approximate #fault #logic #synthesis: Approximate logic synthesis for error tolerant applications (DS, SKG), pp. 957–960.
DATE-DF-2006-NazarianPGB #named #set #statistics: STAX: statistical crosstalk target set compaction (SN, MP, SKG, MAB), pp. 172–177.
DAC-2001-ChenGB: A New Gate Delay Model for Simultaneous Switching and Its Applications (LCC, SKG, MAB), pp. 289–294.
DATE-2001-QuasemG #fault #simulation: Exact fault simulation for systems on Silicon that protects each core’s intellectual property (MSQ, SKG), p. 804.
DAC-1998-ParulkarGB #behaviour: Introducing Redundant Computations in a Behavior for Reducing BIST Resources (IP, SKG, MAB), pp. 548–553.
DATE-1998-ParulkarGB #scheduling: Scheduling and Module Assignment for Reducing Bist Resources (IP, SKG, MAB), pp. 66–73.
DAC-1997-WangG #testing: ATPG for Heat Dissipation Minimization During Scan Testing (SW, SKG), pp. 614–619.
DAC-1996-ChenG #fault #generative #satisfiability: A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts (CAC, SKG), pp. 209–214.
DAC-1996-ParulkarGB #bound #data flow #graph: Lower Bounds on Test Resources for Scheduled Data Flow Graphs (IP, SKG, MAB), pp. 143–148.
DAC-1995-ParulkarGB #design: Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead (IP, SKG, MAB), pp. 395–401.
DAC-1994-FangG #low cost #testing: Clock Grouping: A Low Cost DFT Methodology for Delay Testing (WCF, SKG), pp. 94–99.
EDAC-1994-ChenG #generative #testing: BIST Test Pattern Generators for Stuck-Open and Delay Testing (CAC, SKG), pp. 289–296.
EDAC-1994-LinGB #generative #low cost #novel: A Low Cost BIST Methodology and Associated Novel Test Pattern Generator (SPL, SKG, MAB), pp. 106–112.
DAC-1993-SrinivasanGB #clustering #performance #pseudo #testing: An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing (RS, SKG, MAB), pp. 242–248.