BibSLEIGH — Kurt

Travelled to:

1 × Finland
1 × France
1 × Germany
19 × USA

Collaborated with:

S.Devadas ∅ D.G.Chinnery S.Malik B.C.Catanzaro W.Wolf A.R.Wang A.L.Sangiovanni-Vincentelli F.Fallah M.Orshansky S.Y.Liao S.W.K.Tjiang A.J.d.Geus M.Garland B.Su N.Sundaram N.Satish K.Ravindran B.Nikolic M.R.Prasad P.Chong P.Vanbekbergen K.Cheng L.Lavagno A.Saldanha J.Akella M.Gries C.Kulkarni C.Sauer P.Schaumont I.Verbauwhede M.Sarrafzadeh A.Ghosh J.White R.Dahlberg R.Bingham W.C.Rhines R.Camposano J.Fiddler J.Lansford A.Wang F.Bacchini G.Spirakis J.A.Carballo F.Hsu K.Yamada M.Sgroi M.Sheets A.Mihal J.M.Rabaey S.S.Sapatnekar E.Haritan A.Devgan D.Kirkpatrick S.Meier D.Pryor T.Spyrou R.Goldman C.Bittlestone A.Bootehsaz S.Y.Borkar E.Chen L.Scheffer C.Visweswariah G.Smith D.Nadamuni R.Chapman J.Fogelin G.Martin B.Bailey

Talks about:

synthesi (7) design (6) asic (6) circuit (5) logic (5) delay (5) generat (4) system (4) optim (4) embed (4)

Person: Kurt Keutzer

DBLP: Keutzer:Kurt

Contributed to:

2011

2008

2007

2005

2004

2003

2002

2001

2000

1999

1998

1995

1994

1992

1991

1990

1989

1988

1987

Wrote 35 papers:

PPoPP-2011-CatanzaroGK #compilation #embedded #named #parallel: Copperhead: compiling an embedded data parallel language (BCC, MG, KK), pp. 47–56.
DAC-2008-CatanzaroKS #research: Parallelizing CAD: a timely research agenda for EDA (BCC, KK, BYS), pp. 12–17.
DAC-2008-SapatnekarHKDKMPS #manycore: Reinventing EDA with manycore processors (SSS, EH, KK, AD, DK, SM, DP, TS), pp. 126–127.
ICML-2008-CatanzaroSK #classification #performance: Fast support vector machine training and classification on graphics processors (BCC, NS, KK), pp. 104–111.
DAC-2007-BacchiniSCKGHY #roadmap: Megatrends and EDA 2017 (FB, GS, JAC, KK, AJdG, FCH, KY), pp. 21–22.
DATE-2007-SatishRK #approach #communication #constraints #graph #multi #optimisation #scheduling: A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors (NS, KR, KK), pp. 57–62.
DAC-2005-ChinneryK #perspective: Closing the power gap between ASIC and custom: an ASIC perspective (DGC, KK), pp. 275–280.
DAC-2004-DahlbergKBGR #named: EDA: this is serious business (RD, KK, RB, AJdG, WCR), p. 1.
DAC-2004-GoldmanKBBBCSV #question #statistics: Is statistical timing statistically significant? (RG, KK, CB, AB, SYB, EC, LS, CV), p. 498.
DATE-2003-GriesKSK #case study #modelling #network #simulation: Comparing Analytical Modeling with Simulation for Network Processors: A Case Study (MG, CK, CS, KK), pp. 20256–20261.
DAC-2002-OrshanskyK #analysis #framework #probability: A general probabilistic framework for worst case timing analysis (MO, KK), pp. 556–561.
DAC-2002-SmithNMCFKMB #embedded #question #tool support: Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? (GS, DN, SM, RC, JF, KK, GM, BB), p. 479.
DAC-2001-ChinneryNK: Achieving 550Mhz in an ASIC Methodology (DGC, BN, KK), pp. 420–425.
DAC-2001-SchaumontVKS #configuration management: A Quick Safari Through the Reconfiguration Jungle (PS, IV, KK, MS), pp. 172–177.
DAC-2001-SgroiSMKMRS #design: Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design (MS, MS, AM, KK, SM, JMR, ALSV), pp. 667–672.
DAC-2000-ChinneyK #perspective: Closing the gap between ASIC and custom: an ASIC perspective (DGC, KK), pp. 637–642.
DAC-1999-CamposanoKFSL #design #embedded: HW and SW in Embedded System Design: Loveboat, Shipwreck, or Ships Passing in the Night (RC, KK, JF, ALSV, JL), pp. 76–77.
DAC-1999-PrasadCK #question #why: Why is ATPG Easy? (MRP, PC, KK), pp. 22–28.
DAC-1998-FallahDK #functional #generative #linear #modelling #programming #satisfiability #using: Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability (FF, SD, KK), pp. 528–533.
DAC-1998-FallahDK98a #functional #metric #named #performance #test coverage #verification: OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification (FF, SD, KK), pp. 152–157.
DAC-1995-LiaoDKTW #embedded #optimisation: Code Optimization Techniques for Embedded DSP Microprocessors (SYL, SD, KK, SWKT, ARW), pp. 599–604.
DAC-1995-VanbekbergenWK #design #validation: A Design and Validation System for Asynchronous Circuits (PV, ARW, KK), pp. 725–730.
PLDI-1995-LiaoDKTW: Storage Assignment to Decrease Code Size (SYL, SD, KK, SWKT, AW), pp. 186–195.
DAC-1994-Keutzer #co-evolution #design: Hardware-Software Co-Design and ESDA (KK), pp. 435–436.
DAC-1992-DevadasKMW #logic #verification: Certified Timing Verification and the Transition Delay of a Logic Circuit (SD, KK, SM, ARW), pp. 549–555.
DAC-1992-GhoshDKW #estimation #process: Estimation of Average Switching Activity in Combinational and Sequential Circuits (AG, SD, KK, JW), pp. 253–259.
DAC-1991-ChengDK #design #generative #robust #standard #synthesis #testing: Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology (KTC, SD, KK), pp. 80–86.
DAC-1991-DevadasKM #algorithm #generative #multi #testing: A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults (SD, KK, SM), pp. 359–365.
DAC-1991-LavagnoKS #algorithm #synthesis: Algorithms for Synthesis of Hazard-Free Asynchronous Circuits (LL, KK, ALSV), pp. 302–308.
DAC-1990-DevadasK #logic #optimisation #robust #synthesis: Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits (SD, KK), pp. 221–227.
DAC-1990-KeutzerMS: Is Redundancy Necessary to Reduce Delay (KK, SM, AS), pp. 228–234.
DAC-1989-Keutzer #architecture #design #generative #logic #synthesis: Three Competing Design Methodologies for ASIC’s: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation (KK), pp. 308–313.
DAC-1988-WolfKA #algorithm #kernel #logic #multi: A Kernel-Finding State Assignment Algorithm for Multi-Level Logic (WW, KK, JA), pp. 433–438.
PLDI-1988-KeutzerW #compilation #hardware: Anatomy of a Hardware Compiler (KK, WW), pp. 95–104.
DAC-1987-Keutzer #graph #named #optimisation: DAGON: Technology Binding and Local Optimization by DAG Matching (KK), pp. 341–347.