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Travelled to:
1 × France
3 × Germany
5 × USA
Collaborated with:
F.Balarin X.Chen A.L.Sangiovanni-Vincentelli Y.Watanabe L.Lavagno A.Jurecska R.Mannion S.Cotterell F.Vahid G.Yang A.Davare Y.Luo L.N.Bhuyan J.Yu W.Wu J.Yang M.Chiodo P.Giusto K.Suzuki E.Sentovich
Talks about:
system (6) network (4) design (4) simul (3) embed (3) base (3) constraint (2) processor (2) synthesi (2) automat (2)

Person: Harry Hsieh

DBLP DBLP: Hsieh:Harry

Contributed to:

DATE 20062006
DAC 20052005
DATE 20052005
DATE DF 20042004
DAC 20032003
DATE 20032003
DAC 20002000
DAC 19961996
DAC 19951995

Wrote 10 papers:

DATE-2006-YangCBHS #communication #framework #integration
Communication and co-simulation infrastructure for heterogeneous system integration (GY, XC, FB, HH, ALSV), pp. 462–467.
DAC-2005-ChenDHSW #analysis #concurrent #design #simulation
Simulation based deadlock analysis for system level designs (XC, AD, HH, ALSV, YW), pp. 260–265.
DATE-2005-MannionHCV #network #programmable #synthesis
System Synthesis for Networks of Programmable Blocks (RM, HH, SC, FV), pp. 888–893.
DATE-2005-YuWCHYB #architecture #design #network
Assertion-Based Design Exploration of DVS in Network Processor Architectures (JY, WW, XC, HH, JY, FB), pp. 92–97.
DATE-DF-2004-ChenLHBB #design #network
Utilizing Formal Assertions for System Design of Network Processors (XC, YL, HH, LNB, FB), pp. 126–133.
DAC-2003-ChenHBW #analysis #automation #constraints #logic
Automatic trace analysis for logic of constraints (XC, HH, FB, YW), pp. 460–465.
DATE-2003-ChenHBW #automation #constraints #generative #monitoring #simulation
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula (XC, HH, FB, YW), pp. 11174–11175.
DAC-2000-HsiehBLS #design #embedded #performance
Efficient methods for embedded system design space exploration (HH, FB, LL, ALSV), pp. 607–612.
DAC-1996-BalarinHJLS #embedded #network #verification
Formal Verification of Embedded Systems based on CFSM Networks (FB, HH, AJ, LL, ALSV), pp. 568–571.
DAC-1995-ChiodoGJLHSSS #embedded #source code #synthesis
Synthesis of Software Programs for Embedded Control Applications (MC, PG, AJ, LL, HH, KS, ALSV, ES), pp. 587–592.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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