Travelled to:4 × Germany
9 × USA
Collaborated with:X.Liu E.G.Friedman K.N.Lalgudi Y.Peng K.H.Randall D.Velenis S.Kim C.H.Ziesler M.Potkonjak A.Raghavan K.P.Pipe T.F.Wenisch M.M.K.Martin L.Emurian L.Shao Y.Luo A.Chandawalla
Talks about:delay (5) power (4) perform (3) repeat (3) clock (3) high (3) low (3) sprint (2) insert (2) effici (2)
Person: Marios C. Papaefthymiou
DBLP: Papaefthymiou:Marios_C=
Contributed to:
2013
2012
2005
2004200320022001200119991999199619951993Wrote 13 papers:
- ASPLOS-2013-RaghavanESPPWM #hardware #testing
- Computational sprinting on a hardware/software testbed (AR, LE, LS, MCP, KPP, TFW, MMKM), pp. 155–166.
- HPCA-2012-RaghavanLCPPWM
- Computational sprinting (AR, YL, AC, MCP, KPP, TFW, MMKM), pp. 249–260.
- DATE-2005-LiuPP #hybrid #named #performance #power management
- RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power (XL, YP, MCP), pp. 1330–1335.
- DAC-2004-LiuPP #library #power management #question #what
- Practical repeater insertion for low power: what repeater library do we need? (XL, YP, MCP), pp. 30–35.
- DATE-2003-VelenisPF #network #nondeterminism #performance
- Reduced Delay Uncertainty in High Performance Clock Distribution Networks (DV, MCP, EGF), pp. 10068–10075.
- DAC-2002-LiuP #design #power management
- Design of a high-throughput low-power IS95 Viterbi decoder (XL, MCP), pp. 263–268.
- DAC-2001-KimZP #multi
- A True Single-Phase 8-bit Adiabatic Multiplier (SK, CHZ, MCP), pp. 758–763.
- DATE-2001-LiuP #design #estimation
- A static power estimation methodolodgy for IP-based design (XL, MCP), pp. 280–289.
- DAC-1999-LiuPF #performance #scheduling
- Maximizing Performance by Retiming and Clock Skew Scheduling (XL, MCP, EGF), pp. 231–236.
- DATE-1999-LiuPF
- Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits (XL, MCP, EGF), pp. 643–649.
- DAC-1996-LalgudiPP #effectiveness #optimisation #problem
- Optimizing Systems for Effective Block-Processing: The k-Delay Problem (KNL, MCP, MP), pp. 714–719.
- DAC-1995-LalgudiP #modelling #named #performance
- DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling (KNL, MCP), pp. 304–309.
- DAC-1993-PapaefthymiouR #named
- TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry (MCP, KHR), pp. 497–502.