BibSLEIGH corpus
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Travelled to:
3 × USA
4 × Germany
7 × France
Collaborated with:
M.S.Reorda F.Corno S.D.Carlo A.Benso G.D.Natale S.Chiusano M.Rebaudengo M.Indaco H.Wunderlich P.Camurati S.Gai C.Zambelli P.Olivo D.Bertozzi E.I.Vatajelu S.Cataldo M.Violante M.Gilli F.Somenzi M.Mezzalama A.Bosio A.Baldini S.Mo A.Taddei R.Ubar C.Bayol B.Soulas E.I.Vatajelu R.Rodríguez-Montañés M.Renovell J.Figueras E.M.Rudnick R.Vietti A.Ellis G.Cabodi M.Fabiano M.A.Kochte C.G.Zoellin M.E.Imhof R.S.Khaligh M.Radetzki L.Zuolo R.Micheloni S.Galfano Y.Zorian J.P.Teixeira I.C.Teixeira C.E.Pereira O.P.Dias J.Semião P.Muhmenthaler W.Radermacher
Talks about:
test (9) level (6) generat (5) model (5) new (5) techniqu (4) circuit (4) sequenti (3) symbol (3) explor (3)

Person: Paolo Prinetto

DBLP DBLP: Prinetto:Paolo

Contributed to:

DATE 20152015
DATE 20142014
DATE 20122012
DATE 20092009
DATE 20062006
DATE 20022002
DATE 20012001
DATE 20002000
DATE 19981998
ED&TC 19971997
SAC 19971997
DAC 19921992
CAV 19901990
DAC 19831983

Wrote 22 papers:

STT MRAM-Based PUFs (EIV, GDN, MI, PP), pp. 872–875.
DATE-2015-VatajeluRIRPF #estimation #metric #robust
Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell (EIV, RRM, MI, MR, PP, JF), pp. 447–452.
DATE-2014-ZuoloZMGICPOB #design #fine-grained #framework #named
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives (LZ, CZ, RM, SG, MI, SDC, PP, PO, DB), pp. 1–6.
DATE-2012-ZambelliIFCPOB #approach #trade-off
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories (CZ, MI, MF, SDC, PP, PO, DB), pp. 881–886.
DATE-2009-KochteZIKRWCP #modelling #transaction #using #validation
Test exploration and validation using transaction level models (MAK, CGZ, MEI, RSK, MR, HJW, SDC, PP), pp. 1250–1253.
DATE-2006-BensoBCNP #automation #fault #testing
Automatic march tests generations for static linked faults in SRAMs (AB, AB, SDC, GDN, PP), pp. 1258–1263.
DATE-2002-BaldiniBPMT #functional #uml
Beyond UML to an End-of-Line Functional Test Engine (AB, AB, PP, SM, AT), pp. 499–503.
DATE-2002-BensoCNP #algorithm #automation #generative #testing
An Optimal Algorithm for the Automatic Generation of March Tests (AB, SDC, GDN, PP), pp. 938–943.
DATE-2001-BensoCNP #analysis #distributed #fault #injection #open source
SEU effect analysis in an open-source router via a distributed fault injection environment (AB, SDC, GDN, PP), pp. 219–225.
DATE-2001-ChiusanoCPW #on the #set
On applying the set covering model to reseeding (SC, SDC, PP, HJW), pp. 156–161.
DATE-2001-ZorianPTTPDSMR #embedded #tutorial
Embedded tutorial: TRP: integrating embedded test and ATE (YZ, PP, JPT, ICT, CEP, OPD, JS, PM, WR), pp. 34–37.
DATE-2000-CataldoCPW #functional #generative #hardware
Optimal Hardware Pattern Generation for Functional BIST (SC, SC, PP, HJW), pp. 292–297.
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection (FC, PP, MSR, MV), pp. 670–677.
DATE-1998-RudnickVECPR #generative #performance #testing #using
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques (EMR, RV, AE, FC, PP, MSR), pp. 570–576.
EDTC-1997-BensoPRRU #approach #fault #graph #low level
A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs (AB, PP, MR, MSR, RU), pp. 560–565.
EDTC-1997-ChiusanoCPR #graph #hybrid #problem
Hybrid symbolic-explicit techniques for the graph coloring problem (SC, FC, PP, MSR), pp. 422–426.
EDTC-1997-CornoPRR #sequence #testing
New static compaction techniques of test sequences for sequential circuits (FC, PP, MR, MSR), pp. 37–43.
SAC-1997-CornoPRR #algorithm #generative #named
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits (FC, PP, MR, MSR), pp. 228–232.
EDAC-1994-CamuratiCPBS #design #modelling #verification
System-Level Modeling and Verification: a Comprehensive Design Methodology (PC, FC, PP, CB, BS), pp. 636–640.
DAC-1992-CabodiCCGPR #traversal
A New Model for Improving symbolic Product Machine Traversal (GC, PC, FC, SG, PP, MSR), pp. 614–619.
CAV-1990-CamuratiGPR #model checking #using
The Use of Model Checking in ATPG for Sequential Circuits (PC, MG, PP, MSR), pp. 86–95.
DAC-1983-SomenziGMP #testing #verification
A new integrated system for PLA testing and verification (FS, SG, MM, PP), pp. 57–63.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.