BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × France
4 × Germany
5 × USA
Collaborated with:
X.Zhang D.Forte N.Ahmed V.Jayaram X.Wang R.M.Rad M.T.Rahman N.Tuzzio M.Li A.Davoodi S.Wang L.Winemberg U.Guin J.Fahrny K.Peng M.Yilmaz K.Chakrabarty J.Lee S.Narayan M.Kapralos K.Xiao X.Zhang J.Shi
Talks about:
delay (4) pattern (3) generat (3) chip (3) transit (2) process (2) hardwar (2) variat (2) trojan (2) sensor (2)

Person: Mohammad Tehranipoor

DBLP DBLP: Tehranipoor:Mohammad

Contributed to:

DAC 20142014
DATE 20142014
DAC 20122012
DATE 20122012
DAC 20112011
DATE 20112011
DATE 20102010
DATE 20082008
DAC 20072007
DAC 20062006

Wrote 13 papers:

DAC-2014-GuinZFT #low cost
Low-cost On-Chip Structures for Combating Die and IC Recycling (UG, XZ, DF, MT), p. 6.
DAC-2014-RahmanXFZST #generative #independence #named #random
TI-TRNG: Technology Independent True Random Number Generator (MTR, KX, DF, XZ, JS, MT), p. 6.
DATE-2014-RahmanFFT #design #named
ARO-PUF: An aging-resistant ring oscillator PUF design (MTR, DF, JF, MT), pp. 1–6.
DAC-2012-ZhangTT #identification #using
Identification of recovered ICs using fingerprints from a light-weight on-chip sensor (XZ, NT, MT), pp. 703–708.
DATE-2012-LiDT #authentication #detection #framework #hardware #self
A sensor-assisted self-authentication framework for hardware trojan detection (ML, AD, MT), pp. 1331–1336.
DAC-2011-WangTW #metric #optimisation
In-field aging measurement and calibration for power-performance optimization (SW, MT, LW), pp. 706–711.
DATE-2011-ZhangT #detection #hardware #named #network
RON: An on-chip ring oscillator network for hardware Trojan detection (XZ, MT), pp. 1638–1643.
DATE-2010-PengYTC #fault #process
High-quality pattern selection for screening small-delay defects considering process variations and crosstalk (KP, MY, MT, KC), pp. 1426–1431.
DATE-2010-WangT #novel #physics #process
Novel Physical Unclonable Function with process and environmental variations (XW, MT), pp. 1065–1070.
DATE-2008-LeeNKT #fault #generative
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation (JL, SN, MK, MT), pp. 1172–1177.
DAC-2007-AhmedTJ #design #fault #generative
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design (NA, MT, VJ), pp. 533–538.
DAC-2006-AhmedTJ #fault
Timing-based delay test for screening small delay defects (NA, MT, VJ), pp. 320–325.
DAC-2006-RadT #clustering #hybrid
A new hybrid FPGA with nanoscale clusters and CMOS routing (RMR, MT), pp. 727–730.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.