Travelled to:1 × Germany
3 × France
4 × USA
Collaborated with:F.Vahid K.Shankar ∅ S.X.Tan C.Zhang G.Stitt S.Cotterell T.Givargis
Talks about:dynam (5) softwar (3) hardwar (3) partit (3) fpga (3) architectur (2) processor (2) system (2) profil (2) applic (2)
Person: Roman L. Lysecky
DBLP: Lysecky:Roman_L=
Contributed to:
2009
2007200520042004200320022000Wrote 10 papers:
- DAC-2009-ShankarL #multi #profiling
- Non-intrusive dynamic application profiling for multitasked applications (KS, RLL), pp. 130–135.
- DATE-2007-Lysecky #embedded #performance #power management
- Low-power warp processor for power efficient high-performance embedded systems (RLL), pp. 141–146.
- DATE-2005-LyseckyV #case study #clustering #hardware #using
- A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning (RLL, FV), pp. 18–23.
- DAC-2004-LyseckyVT #compilation
- Dynamic FPGA routing for just-in-time FPGA compilation (RLL, FV, SXDT), pp. 954–959.
- DATE-v1-2004-LyseckyV #architecture #clustering #configuration management #hardware #logic
- A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning (RLL, FV), pp. 480–485.
- DATE-v1-2004-ZhangVL #architecture #embedded #self
- A Self-Tuning Cache Architecture for Embedded Systems (CZ, FV, RLL), pp. 142–147.
- DAC-2003-LyseckyV #logic
- On-chip logic minimization (RLL, FV), pp. 334–337.
- DAC-2003-StittLV #approach #clustering #hardware
- Dynamic hardware/software partitioning: a first approach (GS, RLL, FV), pp. 250–255.
- DAC-2002-LyseckyCV #memory management #performance #profiling
- A fast on-chip profiler memory (RLL, SC, FV), pp. 28–33.
- DATE-2000-LyseckyVG #latency
- Techniques for Reducing Read Latency of Core Bus Wrappers (RLL, FV, TG), pp. 84–91.