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Travelled to:
1 × Spain
2 × France
3 × USA
Collaborated with:
M.Martonosi D.M.Brooks G.Hoang R.B.Findler Z.Hu F.Lu G.Trajcevski S.Liu L.Zhang L.S.Bai R.P.Dick L.Shang M.S.Gupta J.L.Oatley G.Wei
Talks about:
variat (3) multiprocessor (2) character (2) wavelet (2) voltag (2) chip (2) microprocessor (1) architectur (1) understand (1) processor (1)

Person: Russ Joseph

DBLP DBLP: Joseph:Russ

Contributed to:

ASPLOS 20112011
DATE 20112011
DAC 20092009
DATE 20072007
HPCA 20042004
HPCA 20032003

Wrote 6 papers:

ASPLOS-2011-HoangFJ #compilation
Exploring circuit timing-aware language and compilation (GH, RBF, RJ), pp. 345–356.
DATE-2011-LuJTL #architecture #parametricity #performance #simulation
Efficient parameter variation sampling for architecture simulations (FL, RJ, GT, SL), pp. 1578–1583.
DAC-2009-ZhangBDSJ #multi #process
Process variation characterization of chip-level multiprocessors (LZ, LSB, RPD, LS, RJ), pp. 694–697.
DATE-2007-GuptaOJWB #comprehension #distributed #multi #network #using
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network (MSG, JLO, RJ, GYW, DMB), pp. 624–629.
HPCA-2004-JosephHM #analysis #case study #design #experience
Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization (RJ, ZH, MM), pp. 36–47.
HPCA-2003-JosephBM #performance
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors (RJ, DMB, MM), pp. 79–90.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.