Travelled to:1 × Spain
2 × France
3 × USA
Collaborated with:M.Martonosi D.M.Brooks G.Hoang R.B.Findler Z.Hu F.Lu G.Trajcevski S.Liu L.Zhang L.S.Bai R.P.Dick L.Shang M.S.Gupta J.L.Oatley G.Wei
Talks about:variat (3) multiprocessor (2) character (2) wavelet (2) voltag (2) chip (2) microprocessor (1) architectur (1) understand (1) processor (1)
Person: Russ Joseph
DBLP: Joseph:Russ
Contributed to:
2011
2011
20092007
20042003Wrote 6 papers:
- ASPLOS-2011-HoangFJ #compilation
- Exploring circuit timing-aware language and compilation (GH, RBF, RJ), pp. 345–356.
- DATE-2011-LuJTL #architecture #parametricity #performance #simulation
- Efficient parameter variation sampling for architecture simulations (FL, RJ, GT, SL), pp. 1578–1583.
- DAC-2009-ZhangBDSJ #multi #process
- Process variation characterization of chip-level multiprocessors (LZ, LSB, RPD, LS, RJ), pp. 694–697.
- DATE-2007-GuptaOJWB #comprehension #distributed #multi #network #using
- Understanding voltage variations in chip multiprocessors using a distributed power-delivery network (MSG, JLO, RJ, GYW, DMB), pp. 624–629.
- HPCA-2004-JosephHM #analysis #case study #design #experience
- Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization (RJ, ZH, MM), pp. 36–47.
- HPCA-2003-JosephBM #performance
- Control Techniques to Eliminate Voltage Emergencies in High Performance Processors (RJ, DMB, MM), pp. 79–90.