BibSLEIGH — Li

Travelled to:

1 × Chile
1 × Japan
1 × United Kingdom
2 × France
3 × Germany
5 × USA

Collaborated with:

R.P.Dick N.K.Jha W.Zhang L.Peh X.Chen R.G.Knobel Z.Li D.Li Q.Lv Y.Lu H.Zhou X.Zeng C.Zhu Z.(.Gu A.A.M.Bsoul N.Manjikian N.Allec A.R.Mickelson Y.Sun N.Gu Y.Liu H.Yang A.Kumar C.Chen Y.Zhao M.Mohamed L.Zhang L.S.Bai R.Joseph J.Wu Y.Yang H.Zhu F.Yang M.Dong L.Yin W.Deng Q.Wang C.Yuan J.Guo L.Ma D.Fay M.Vachharajani D.Filipovic W.Park

Talks about:

dynam (5) chip (5) power (4) architectur (3) thermal (3) reliabl (3) process (3) network (3) analysi (3) variat (3)

Person: Li Shang

DBLP: Shang:Li

Contributed to:

2015

2012

2011

2010

2009

2008

2007

2006

2003

Wrote 19 papers:

SIGIR-2015-ChenLZLS #approximate #matrix #named #recommendation #scalability: WEMAREC: Accurate and Scalable Recommendation through Weighted and Ensemble Matrix Approximation (CC, DL, YZ, QL, LS), pp. 303–312.
ICPR-2012-DongYDWYGSM #classification #linear: A Linear Max K-min classifier (MD, LY, WD, QW, CY, JG, LS, LM), pp. 2967–2971.
CIKM-2011-LiLSG #community #named #online #performance #privacy #recommendation #social: YANA: an efficient privacy-preserving recommender system for online social communities (DL, QL, LS, NG), pp. 2269–2272.
DAC-2011-LiMCMS #modelling #network #performance #reliability #simulation: Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance (ZL, MM, XC, ARM, LS), pp. 735–740.
DATE-2010-BsoulMS #process: Reliability- and process variation-aware placement for FPGAs (AAMB, NM, LS), pp. 1809–1814.
DATE-2010-ChenDS #algorithm #analysis: Properties of and improvements to time-domain dynamic thermal analysis algorithms (XC, RPD, LS), pp. 1165–1170.
DAC-2009-LiFMSVFPS #hybrid #named #network: Spectrum: a hybrid nanophotonic-electric on-chip network (ZL, DF, ARM, LS, MV, DF, WP, YS), pp. 575–580.
DAC-2009-LuSZZYZ #analysis #process #reliability #statistics: Statistical reliability analysis under process variation and aging effects (YL, LS, HZ, HZ, FY, XZ), pp. 514–519.
DAC-2009-LuZSZ #algorithm #manycore #parallel: Multicore parallel min-cost flow algorithm for CAD applications (YL, HZ, LS, XZ), pp. 832–837.
DAC-2009-ZhangBDSJ #multi #process: Process variation characterization of chip-level multiprocessors (LZ, LSB, RPD, LS, RJ), pp. 694–697.
DATE-2009-LiWSDS #communication #latency: Latency criticality aware on-chip communication (ZL, JW, LS, RPD, YS), pp. 1052–1057.
DATE-2008-AllecKS #adaptation #simulation: Adaptive Simulation for Single-Electron Devices (NA, RGK, LS), pp. 1021–1026.
DAC-2007-ZhangSJ #architecture #configuration management #design #hybrid #named #optimisation: NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture (WZ, LS, NKJ), pp. 300–305.
DAC-2007-ZhuGSDK #architecture #power management #towards #using: Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors (CZ, Z(G, LS, RPD, RGK), pp. 312–317.
DATE-2007-LiuDSY #estimation #power management: Accurate temperature-dependent integrated circuit leakage power estimation is easy (YL, RPD, LS, HY), pp. 1526–1531.
DAC-2006-KumarSPJ #approach #coordination #named: HybDTM: a coordinated hardware-software approach for dynamic thermal management (AK, LS, LSP, NKJ), pp. 548–553.
DAC-2006-ZhangJS #architecture #configuration management #hybrid #named: NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture (WZ, NKJ, LS), pp. 711–716.
DATE-2006-YangGZSD #adaptation #analysis #design #synthesis: Adaptive chip-package thermal analysis for synthesis and design (YY, Z(G, CZ, LS, RPD), pp. 844–849.
HPCA-2003-ShangPJ #network #optimisation #scalability: Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks (LS, LSP, NKJ), pp. 91–102.