BibSLEIGH — Ramesh

Travelled to:

12 × USA
3 × France
3 × Germany

Collaborated with:

A.Orailoglu K.Wu J.Rajendran O.Sinanoglu K.Kim A.Dasgupta W.Rao B.Yang M.Potkonjak X.Wang X.Guo Y.Pino B.Iyer V.Vedula D.A.McGrew D.Chang S.Ozev P.Mishra Y.Kim

Talks about:

synthesi (6) level (6) fault (6) detect (5) base (5) architectur (4) secur (4) logic (4) microarchitectur (3) design (3)

Person: Ramesh Karri

DBLP: Karri:Ramesh

Contributed to:

2015

2014

2013

2012

2007

2006

2005

2004

2002

2001

1997

1996

1994

1993

1992

Wrote 22 papers:

DAC-2015-RajendranVK #detection: Detecting malicious modifications of data in third-party intellectual property cores (JR, VV, RK), p. 6.
DATE-2014-ChangOSK #approximate #estimation #statistics: Approximating the age of RF/analog circuits through re-characterization and statistical estimation (DC, SO, OS, RK), pp. 1–4.
DAC-2013-WangK #control flow #detection #hardware #kernel #named #performance #using: NumChecker: detecting kernel control-flow modifying rootkits by using hardware performance counters (XW, RK), p. 7.
DATE-2013-RajendranSK #question: Is split manufacturing secure? (JR, OS, RK), pp. 1259–1264.
DAC-2012-GuoK #concurrent #detection #encryption #fault #standard: Invariance-based concurrent error detection for advanced encryption standard (XG, RK), pp. 573–578.
DAC-2012-RajendranPSK #analysis #logic #obfuscation #security: Security analysis of logic obfuscation (JR, YP, OS, RK), pp. 83–89.
DATE-2012-RajendranPSK #analysis #encryption #fault #logic #perspective: Logic encryption: A fault analysis perspective (JR, YP, OS, RK), pp. 953–958.
DATE-2007-RaoOK #fault tolerance #interactive #logic: Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs (WR, AO, RK), pp. 865–869.
DAC-2006-RaoOK #architecture #logic: Topology aware mapping of logic functions onto nanowire-based crossbar architectures (WR, AO, RK), pp. 723–726.
DAC-2005-YangWK #architecture: Secure scan: a design-for-test architecture for crypto chips (BY, KW, RK), pp. 135–140.
DATE-2005-KimWK #architecture #design #robust: owards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths (KK, KW, RK), pp. 1214–1219.
DAC-2004-YangKM #architecture #named #optimisation: Divide-and-concatenate: an architecture level optimization technique for universal hash functions (BY, RK, DAM), pp. 614–617.
DATE-2002-WuK #algorithm: Exploiting Idle Cycles for Algorithm Level Re-Computing (KW, RK), pp. 842–846.
DAC-2001-KarriWMK #concurrent #detection #fault #symmetry: Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers (RK, KW, PM, YK), pp. 579–585.
DAC-1997-KimKP #programmable #synthesis: Synthesis of Application Specific Programmable Processors (KK, RK, MP), pp. 353–358.
DAC-1997-PotkonjakKK #behaviour #case study #design: Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study (MP, KK, RK), pp. 252–257.
DAC-1996-DasguptaK #process #reliability: Electromigration Reliability Enhancement via Bus Activity Distribution (AD, RK), pp. 353–356.
DAC-1996-DasguptaK96a #order #reliability: Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing (AD, RK), pp. 819–824.
DAC-1996-IyerK #architecture #named #self #synthesis: Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis (BI, RK), pp. 137–142.
DAC-1994-KarriO #architecture #detection #fault #self #synthesis: Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis (RK, AO), pp. 552–556.
DAC-1993-KarriO #architecture #synthesis: High-Level Synthesis of Fault-Secure Microarchitectures (RK, AO), pp. 429–433.
DAC-1992-KarriO #fault tolerance #synthesis: Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs (RK, AO), pp. 662–665.