Travelled to:1 × Germany
2 × France
4 × USA
Collaborated with:M.R.Mercer R.Kapur ∅ E.B.Eichelberger B.Underwood N.Oh J.Sproch J.T.d.Sousa F.M.Gonçalves J.P.Teixeira J.Liou L.Wang K.Cheng J.Dworak
Talks about:test (4) testabl (2) design (2) logic (2) fault (2) delay (2) use (2) interdepend (1) architectur (1) structur (1)
Person: Thomas W. Williams
DBLP: Williams:Thomas_W=
Contributed to:
2003
200220021994199119821977Wrote 7 papers:
- DATE-2003-OhKWS #architecture #feedback #using
- Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture (NO, RK, TWW, JS), pp. 10110–10115.
- DAC-2002-LiouWCDMKW #fault #multi #performance #testing #using
- Enhancing test efficiency for delay fault testing using multiple-clocked schemes (JJL, LCW, KTC, JD, MRM, RK, TWW), pp. 371–374.
- DATE-2002-KapurWM #logic
- Directed-Binary Search in Logic BIST Diagnostics (RK, TWW, MRM), p. 1121.
- EDAC-1994-SousaGTW #fault #modelling
- Fault Modeling and Defect Level Projections in Digital ICs (JTdS, FMG, JPT, TWW), pp. 436–442.
- DAC-1991-WilliamsUM #network #testing
- The Interdependence Between Delay-Optimization of Synthesized Networks and Testing (TWW, BU, MRM), pp. 87–92.
- DAC-1982-Williams #design #testing
- Design for testability (TWW), p. 9.
- DAC-1977-EichelbergerW #design #logic #testing
- A logic design structure for LSI testability (EBE, TWW), pp. 462–468.