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Travelled to:
1 × France
7 × USA
Collaborated with:
Z.D.Umrigar M.E.Dalkiliç S.Ganguly V.Narayanan E.P.Stabler P.Mayor N.Radia S.R.Nassif N.Rodriguez D.Sylvester C.Bittlestone R.Radojcic N.Ns J.C.Rey J.Kawa R.C.Aitken C.Lütkemeyer A.J.Strojwas S.Trimberger
Talks about:
connect (2) machin (2) formal (2) design (2) verif (2) simul (2) fault (2) algorithm (1) parallel (1) diagnosi (1)

Person: Vijay Pitchumani

DBLP DBLP: Pitchumani:Vijay

Contributed to:

DAC 20102010
DAC 20062006
DAC 19911991
DAC 19891989
SLP 19851985
DAC 19831983
DAC 19821982

Wrote 9 papers:

DAC-2010-NSRKALPST #problem #question #variability
Who solves the variability problem? (NN, JCR, JK, RCA, CL, VP, AJS, ST), pp. 218–219.
DAC-2006-NassifPRSBR #analysis #question
Variation-aware analysis: savior of the nanometer era? (SRN, VP, NR, DS, CB, RR), pp. 411–412.
EDAC-1994-DalkilicP #bound #scheduling #using
Optimal Operation Scheduling Using Resource Lower Bound Estimations (MED, VP), pp. 319–324.
DAC-1991-PitchumaniMR #fault #simulation
A System for Fault Diagnosis and Simulation of VHDL Descriptions (VP, PM, NR), pp. 144–150.
Compaction of a Routed Channel on the Connection Machine (SG, VP), pp. 779–782.
DAC-1989-NarayananP #algorithm #fault #parallel #simulation
A Massively Parallel Algorithm for Fault Simulation on the Connection Machine (VN, VP), pp. 734–737.
SLP-1985-UmrigarP85 #empirical #first-order #logic #programming
An Experiment in Programming with Full First-Order Logic (ZDU, VP), pp. 40–47.
DAC-1983-UmrigarP #design #hardware #realtime #verification
Formal verification of a real-time hardware design (ZDU, VP), pp. 221–227.
DAC-1982-PitchumaniS #design #formal method #verification
A formal method for computer design verification (VP, EPS), pp. 809–814.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.