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Travelled to:
3 × France
3 × Germany
7 × USA
Collaborated with:
Z.Li M.W.Tian D.Lungeanu X.Tan S.Bhattacharya N.Jangkrajarng A.Manthe B.Wan S.X.Tan T.Pi Y.Bourai R.Hartono K.Mayaram J.Lee L.Yuan
Talks about:
circuit (9) analog (8) simul (5) symbol (4) optim (4) nonlinear (3) analysi (3) layout (3) determin (2) parasit (2)

Person: C.-J. Richard Shi

DBLP DBLP: Shi:C==J=_Richard

Contributed to:

DAC 20052005
DATE 20052005
DAC 20042004
DATE v2 20042004
DAC 20032003
DATE 20032003
DAC 20012001
DAC 20002000
DATE 20002000
DAC 19991999
DATE 19991999
DATE 19981998
DAC 19971997

Wrote 14 papers:

DAC-2005-BhattacharyaJS #optimisation
Template-driven parasitic-aware optimization of analog integrated circuit layouts (SB, NJ, CJRS), pp. 644–647.
DATE-2005-LiS #performance #simulation
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation (ZL, CJRS), pp. 752–757.
DAC-2004-BhattacharyaJHS #design #scalability
Correct-by-construction layout-centric retargeting of large analog designs (SB, NJ, RH, CJRS), pp. 139–144.
DATE-v2-2004-WanS #compilation #multi #simulation
Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation (BW, CJRS), pp. 1310–1315.
DAC-2003-MantheLS #analysis
Symbolic analysis of analog circuits with hard nonlinearity (AM, ZL, CJRS), pp. 542–545.
DATE-2003-MantheLSM #analysis
Symbolic Analysis of Nonlinear Analog Circuits (AM, ZL, CJRS, KM), pp. 11108–11109.
DAC-2001-TanS #modelling #network #optimisation #performance
Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling (SXDT, CJRS), pp. 550–554.
DAC-2000-PiS #analysis #approach #diagrams #multi
Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits (TP, CJRS), pp. 19–22.
DATE-2000-BouraiS #layout #optimisation
Layout Compaction for Yield Optimization via Critical Area Minimization (YB, CJRS), pp. 122–125.
DATE-2000-LungeanuS #distributed #parallel #simulation
Parallel and Distributed VHDL Simulation (DL, CJRS), pp. 658–662.
DAC-1999-TanSLLY #linear #network #optimisation #sequence
Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings (XDT, CJRS, DL, JCL, LPY), pp. 78–83.
DATE-1999-TanS #diagrams #scalability #using
Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams (XDT, CJRS), pp. 448–453.
DATE-1998-TianS #fault #performance #simulation
Efficient DC Fault Simulation of Nonlinear Analog Circuits (MWT, CJRS), pp. 899–904.
DAC-1997-TianS #agile #fault #parametricity #simulation
Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances (MWT, CJRS), pp. 275–280.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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