Travelled to:
1 × China
1 × Germany
16 × USA
2 × France
Collaborated with:
C.Delimitrou K.Olukotun D.Sánchez B.D.Carlstrom A.McDonald H.Litz J.Chung D.Lo A.Klimovic ∅ N.G.Bronson M.Dalton H.Kannan P.Ranganathan A.Zmily Mingyu Gao Jing Pu Xuan Yang M.Horowitz A.Adl-Tabatabai J.Casper H.Chafi C.C.Minh A.Belay R.M.Yoo B.Saha N.Zeldovich S.Rivoire M.A.Shah Grant Ayers David Koeplinger Raghu Prabhakar C.Ranger R.Raghuraman A.Penmetsa G.R.Bradski M.Carbin G.Prekas S.Grossman E.Bugnion A.Bittau A.J.Mashtizadeh D.Terei D.Mazières T.Oguntebi S.Hong J.Park S.Park J.D.Balfour D.Black-Schaffer W.J.Dally N.Njoroge S.Wee Y.Teslyar D.Ge D.Dice M.Herlihy N.Shavit C.v.Praun M.L.Scott L.Hammond V.Wong B.Hertzberg M.K.Chen K.J.Brown H.Lee C.D.Sa W.Baek T.Skare Matthew Feldman Yaqi Zhang S.Hadjis Ruben Fiszel T.Zhao Luigi Nardi Ardavan Pedram Qiaoyi Liu Jeff Setter Ankita Nayak Steven Bell Kaidi Cao Heonjae Ha Priyanka Raina
Talks about:
transact (10) memori (8) effici (6) acceler (5) scalabl (4) system (4) schedul (3) resourc (3) program (3) hardwar (3)
Person: Christos Kozyrakis
DBLP: Kozyrakis:Christos
Contributed to:
Wrote 33 papers:
- ASPLOS-2014-DelimitrouK #clustering #named
- Quasar: resource-efficient and QoS-aware cluster management (CD, CK), pp. 127–144.
- HPCA-2014-LoK #manycore
- Dynamic management of TurboMode in modern multi-core chips (DL, CK), pp. 603–613.
- OSDI-2014-BelayPKGKB #latency #named #operating system #throughput
- IX: A Protected Dataplane Operating System for High Throughput and Low Latency (AB, GP, AK, SG, CK, EB), pp. 49–65.
- ASPLOS-2013-DelimitrouK #named #scheduling #semistructured data
- Paragon: QoS-aware scheduling for heterogeneous datacenters (CD, CK), pp. 77–88.
- DATE-2013-Kozyrakis #performance
- Resource efficient computing for warehouse-scale datacenters (CK), pp. 1351–1356.
- HPCA-2012-SanchezK #encoding #flexibility #named #scalability #set
- SCD: A scalable coherence directory with flexible sharer set encoding (DS, CK), pp. 129–140.
- OSDI-2012-BelayBMTMK #cpu #named
- Dune: Safe User-level Access to Privileged CPU Features (AB, AB, AJM, DT, DM, CK), pp. 335–348.
- ASPLOS-2011-CasperOHBKO #hardware #memory management #transaction
- Hardware acceleration of transactional memory on commodity systems (JC, TO, SH, NGB, CK, KO), pp. 27–38.
- ASPLOS-2010-SanchezYK #architecture #flexibility #scheduling
- Flexible architectural support for fine-grain scheduling (DS, RMY, CK), pp. 311–322.
- POPL-2009-BronsonKO #optimisation
- Feedback-directed barrier optimization in a strongly isolated STM (NGB, CK, KO), pp. 213–225.
- HPCA-2008-ChungDKK #memory management #thread #transaction #using
- Thread-safe dynamic binary translation using transactional memory (JC, MD, HK, CK), pp. 279–289.
- OSDI-2008-ZeldovichKDK #hardware #memory management #policy #security #using
- Hardware Enforcement of Application Security Policies Using Tagged Memory (NZ, HK, MD, CK), pp. 225–240.
- DATE-2007-NjorogeCWTGKO #memory management #multi #named #transaction
- ATLAS: a chip-multiprocessor with transactional memory support (NN, JC, SW, YT, DG, CK, KO), pp. 3–8.
- DATE-2007-ParkPBBKD #architecture #embedded #performance #pointer
- Register pointer architecture for efficient embedded processors (JP, SBP, JDB, DBS, CK, WJD), pp. 600–605.
- HPCA-2007-ChafiCCMMBKO #approach #memory management #scalability #transaction
- A Scalable, Non-blocking Approach to Transactional Memory (HC, JC, BDC, AM, CCM, WB, CK, KO), pp. 97–108.
- HPCA-2007-RangerRPBK #manycore #pipes and filters
- Evaluating MapReduce for Multi-core and Multiprocessor Systems (CR, RR, AP, GRB, CK), pp. 13–24.
- PPoPP-2007-Adl-TabatabaiDHSKPS #transaction
- Potential show-stoppers for transactional synchronization (ARAT, DD, MH, NS, CK, CvP, MLS), p. 55.
- PPoPP-2007-Adl-TabatabaiKS #manycore #programming #transaction
- Transactional programming in a multi-core environment (ARAT, CK, BS), p. 272.
- PPoPP-2007-CarlstromMCKO #transaction
- Transactional collection classes (BDC, AM, MC, CK, KO), pp. 56–67.
- SIGMOD-2007-RivoireSRK #benchmark #energy #metric #named
- JouleSort: a balanced energy-efficiency benchmark (SR, MAS, PR, CK), pp. 365–376.
- ASPLOS-2006-ChungMMSCCKO #memory management #trade-off #transaction
- Tradeoffs in transactional memory virtualization (JC, CCM, AM, TS, HC, BDC, CK, KO), pp. 371–381.
- DATE-2006-ZmilyK #embedded #energy #performance
- Simultaneously improving code size, performance, and energy in embedded processors (AZ, CK), pp. 224–229.
- HPCA-2006-ChungCMMCKO #behaviour #parallel #source code #thread #transaction
- The common case transactional behavior of multithreaded programs (JC, HC, CCM, AM, BDC, CK, KO), pp. 266–277.
- ASPLOS-2004-HammondCWHCKO #consistency #programming #transaction
- Programming with transactional coherence and consistency (TCC) (LH, BDC, VW, BH, MKC, CK, KO), pp. 1–13.
- PLDI-2018-KoeplingerFPZHF #compilation #named
- Spatial: a language and compiler for application accelerators (DK, MF, RP, YZ, SH, RF, TZ, LN, AP, CK, KO), pp. 296–311.
- ASPLOS-2016-DelimitrouK #named
- HCloud: Resource-Efficient Provisioning in Shared Cloud Systems (CD, CK), pp. 473–488.
- ASPLOS-2016-PrabhakarKBLSKO #configuration management #generative #hardware #parallel
- Generating Configurable Hardware from Parallel Patterns (RP, DK, KJB, HL, CDS, CK, KO), pp. 651–665.
- ASPLOS-2017-DelimitrouK #in the cloud #named #what
- Bolt: I Know What You Did Last Summer... In The Cloud (CD, CK), pp. 599–613.
- ASPLOS-2017-GaoPYHK #3d #memory management #named #network #performance #scalability
- TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (MG, JP, XY, MH, CK), pp. 751–764.
- ASPLOS-2017-KlimovicLK #named
- ReFlex: Remote Flash ≈ Local Flash (AK, HL, CK), pp. 345–359.
- ASPLOS-2019-GaoYPHK #data flow #named #scalability
- TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators (MG, XY, JP, MH, CK), pp. 807–820.
- ASPLOS-2020-AyersLKR #data access #memory management
- Classifying Memory Access Patterns for Prefetching (GA, HL, CK, PR), pp. 513–526.
- ASPLOS-2020-YangGLSPNBCHRKH #named #scheduling #using
- Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators (XY, MG, QL, JS, JP, AN, SB, KC, HH, PR, CK, MH), pp. 369–383.