BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × Italy
2 × France
9 × USA
Collaborated with:
X.Y.Li S.Dey K.Kozminski H.Lavana M.F.M.Stallmann S.Bhattacharya R.Kuznar B.Zajc B.Rohfleisch M.H.Schultz M.F.Stallmann U.Schlichtmann M.Hermann G.Kedem D.Ghosh N.Kapur J.E.H.III A.Khetawat A.Zemva G.Sakauye A.Lubiw J.Royle R.Epplett J.Tweedale E.S.Y.Shew E.Attfield P.S.Wilcox
Talks about:
partit (3) design (3) applic (3) optim (3) technolog (2) benchmark (2) function (2) circuit (2) effect (2) minim (2)

Person: Franc Brglez

DBLP DBLP: Brglez:Franc

Contributed to:

DAC 20052005
SAT 20032003
SAT 20022002
DAC 20012001
DATE 19981998
DAC 19971997
DAC 19941994
DAC 19931993
DAC 19921992
DAC 19901990
DAC 19871987
DAC 19811981

Wrote 16 papers:

DAC-2005-LiSB #bound #effectiveness #problem
Effective bounding techniques for solving unate and binate covering problems (XYL, MFMS, FB), pp. 385–390.
SAT-2003-LiSB #effectiveness #performance #satisfiability #using
A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation (XYL, MFMS, FB), pp. 53–68.
SAT-2002-BrglezLS #algorithm #benchmark #metric #satisfiability #testing
The role of a skeptic agent in testing and benchmarking of SAT algorithms (FB, XYL, MFS), p. 13.
DAC-2001-BrglezL #design #distributed
A Universal Client for Distributed Networked Design and Computing (FB, HL), pp. 401–406.
DATE-1998-GhoshKBH #benchmark #equivalence #invariant #metric #synthesis
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking (DG, NK, FB, JEHI), pp. 656–663.
DAC-1997-LavanaKBK #collaboration #design #execution #internet #paradigm #workflow
Executable Workflows: A Paradigm for Collaborative Design on the Internet (HL, AK, FB, KK), pp. 553–558.
DAC-1994-BhattacharyaDB #optimisation #resource management
Clock Period Optimization During Resource Sharing and Assignment (SB, SD, FB), pp. 195–200.
DAC-1994-BhattacharyaDB94a #analysis #optimisation #performance #specification
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications (SB, SD, FB), pp. 491–496.
DAC-1994-KuznarBZ #clustering #multi
Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect (RK, FB, BZ), pp. 238–243.
EDAC-1994-RohfleischB #logic #optimisation
Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping (BR, FB), pp. 87–93.
EDAC-1994-ZemvaBKZ #fault
A Functionality Fault Model: Feasibility and Applications (AZ, FB, KK, BZ), pp. 152–158.
DAC-1993-KuznarBK #multi
Cost Minimization of Partitions into Multiple Devices (RK, FB, KK), pp. 315–320.
DAC-1992-SchlichtmannBH #agile
Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping (US, FB, MH), pp. 374–379.
DAC-1990-DeyBK #clustering
Corolla Based Circuit Partitioning and Resynthesis (SD, FB, GK), pp. 607–612.
DAC-1987-SchultzB #fault #simulation
Accelerated Transition Fault Simulation (MHS, FB), pp. 237–243.
DAC-1981-SakauyeLRETSABW #design #set #source code
A set of programs for MOS design (GS, AL, JR, RE, JT, ESYS, EA, FB, PSW), pp. 435–442.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.