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Travelled to:
1 × India
1 × Sweden
1 × Turkey
1 × United Kingdom
13 × USA
2 × Germany
4 × France
Collaborated with:
J.Yang R.Gupta L.Jiang B.Zhao X.Zhang W.Li R.Wang L.Li B.R.Childers C.J.Xue Y.Chen Y.Xu L.Wang P.Zhou E.Mehofer X.Zhang M.Zhao J.Guo J.Zhao J.Zheng Y.Lin Q.Li Q.Li Y.He H.Li L.Gao Y.Du X.Zhou W.Shi J.B.Fryman G.Gu H.S.Lee Chen Li 0015 R.Ausavarungnirun C.J.Rossbach O.Mutlu Yang Guo 0003 Jun Yang 0002
Talks about:
memori (8) effici (5) write (5) phase (4) chang (4) high (4) low (4) process (3) network (3) disturb (3)

Person: Youtao Zhang

DBLP DBLP: Zhang:Youtao

Facilitated 1 volumes:

LCTES 2014Ed

Contributed to:

ASPLOS 20152015
DAC 20152015
DATE 20152015
DAC 20142014
DATE 20132013
LCTES 20132013
DAC 20122012
DATE 20122012
HPCA 20122012
DATE 20112011
DATE 20102010
HPCA 20102010
LCTES 20102010
HPCA 20092009
PLDI 20072007
HPCA 20062006
HPCA 20052005
SAC 20052005
ICSE 20042004
ICSE 20032003
CC 20022002
PLDI 20012001
ASPLOS 20002000
ASPLOS 20192019

Wrote 27 papers:

ASPLOS-2015-WangJZY #memory management #named #reliability
SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance (RW, LJ, YZ, JY), pp. 19–31.
DAC-2015-WangJZWY #energy #performance
Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM (RW, LJ, YZ, LW, JY), p. 6.
DAC-2015-WangJZWY15a #memory management
Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory (RW, LJ, YZ, LW, JY), p. 6.
DATE-2015-ZhangZCY #scalability
Exploiting DRAM restore time variations in deep sub-micron scaling (XZ, YZ, BRC, JY), pp. 477–482.
DAC-2014-ZhaoJZX #process
SLC-enabled Wear Leveling for MLC PCM Considering Process Variation (MZ, LJ, YZ, CJX), p. 6.
DATE-2013-GuoYZC #hybrid #low cost
Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer (JG, JY, YZ, YC), pp. 859–864.
DATE-2013-ZhouZY #design #energy #memory management #network #using
The design of sustainable wireless sensor network node using solar energy and phase change memory (PZ, YZ, JY), pp. 869–872.
LCTES-2013-LiJZHX #compilation #performance #power management
Compiler directed write-mode selection for high performance low power volatile PCM (QL, LJ, YZ, YH, CJX), pp. 101–110.
DAC-2012-JiangZZY #embedded #multi #performance #scalability
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors (LJ, BZ, YZ, JY), pp. 907–912.
DATE-2012-ZhaoYZCL #architecture #array #memory management
Architecting a common-source-line array for bipolar non-volatile memory devices (BZ, JY, YZ, YC, HL), pp. 1451–1454.
HPCA-2012-JiangZZYC #memory management
Improving write operations in MLC phase change memory (LJ, BZ, YZ, JY, BRC), pp. 201–210.
DATE-2011-LiZY
Proactive recovery for BTI in high-k SRAM cells (LL, YZ, JY), pp. 992–997.
DATE-2010-LiZYZ #functional
Proactive NBTI mitigation for busy functional units in out-of-order microprocessors (LL, YZ, JY, JZ), pp. 411–416.
HPCA-2010-XuZZY #throughput
Simple virtual channel allocation for high throughput and high frequency on-chip routers (YX, BZ, YZ, JY), pp. 1–11.
LCTES-2010-LiZ #embedded #mobile #performance
An efficient code update scheme for DSP applications in mobile embedded systems (WL, YZ), pp. 105–114.
HPCA-2009-XuDZZZY #3d #design #network
A low-radix and low-diameter 3D interconnection network design (YX, YD, BZ, XZ, YZ, JY), pp. 30–42.
PLDI-2007-LiZYZ #compilation #energy #named #network #performance
UCC: update-conscious compilation for energy efficiency in wireless sensor networks (WL, YZ, JY, JZ), pp. 383–393.
HPCA-2006-ShiFGLZY #architecture #in memory #memory management #named #security
InfoShield: a security architecture for protecting information usage in memory (WS, JBF, GG, HHSL, YZ, JY), pp. 222–231.
HPCA-2005-ZhangGYZG #memory management #multi #named #security #symmetry
SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors (YZ, LG, JY, XZ, RG), pp. 352–362.
SAC-2005-LinZLY #performance #query #xml
Supporting efficient query processing on compressed XML files (YL, YZ, QL, JY), pp. 660–665.
ICSE-2004-ZhangGZ #diagrams #dynamic analysis #order #performance #slicing #using
Efficient Forward Computation of Dynamic Slices Using Reduced Ordered Binary Decision Diagrams (XZ, RG, YZ), pp. 502–511.
ICSE-2003-ZhangGZ #algorithm #precise #slicing
Precise Dynamic Slicing Algorithms (XZ, RG, YZ), pp. 319–329.
CC-2002-GuptaMZ #analysis #optimisation #representation
A Representation for Bit Section Based Analysis and Optimization (RG, EM, YZ), pp. 62–77.
CC-2002-ZhangG #data type
Data Compression Transformations for Dynamically Allocated Data Structures (YZ, RG), pp. 14–28.
PLDI-2001-ZhangG #representation
Timestamped Whole Program Path Representation and its Applications (YZ, RG), pp. 180–190.
ASPLOS-2000-ZhangYG #design #locality
Frequent Value Locality and Value-Centric Data Cache Design (YZ, JY, RG), pp. 150–159.
ASPLOS-2019-0015ARZMGY #framework #memory management
A Framework for Memory Oversubscription Management in Graphics Processing Units (CL0, RA, CJR, YZ, OM, YG0, JY0), pp. 49–63.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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